HC5549_14 Datasheet, PDF (10/13 Pages) Intersil Corporation – Low Power SLIC with Battery Switch

HC5549
drive to a differential pair which controls the reversal time of
the Tip and Ring DC voltages.
C_POL
=
∆_-----t_--i_--m_-----e_--
75000
(EQ. 30)
Where ∆time is the required reversal time. Polarized
capacitors may be used for C_POL. The low voltage at the
POL pin and minimal voltage excursion ±0.75V, are well
suited to polarized capacitors.
Power Dissipation
The power dissipation equations for forward active operation
also apply to the reverse active mode.
Ringing
Overview
The ringing mode (RNG, 100) provides the low side return
path for externally supplied battery backed ringing. The
ringing signal must be injected through a relay at the ring
terminal. The device should be operated from the low battery
voltage during this mode to minimize the overall power
dissipation during ringing. Current flowing through the Tip
terminal will provide the necessary ring trip information.
Ringing Bias Input
The ringing bias input, VRB, is a high impedance input. The
VRB input is only selected during the ringing mode. The gain
from the VRB input to the Tip output is typically 40V/V. The
following equation shows the relationship of the Tip output
voltage to the VRB input voltage.
V_TIP=
V_-----B_----L_{-- + 40 × VRB}
2
(EQ. 31)
A positive DC voltage at VRB is required to shift the Tip
output voltage towards ground to provide the low side ringing
return path. Tying the logic input F2 to VRB provides the
positive voltage to offset Tip during ringing. A voltage divider
is suggested to provide control the actual voltage applied to VRB.
Logic Control
Ringing patterns consist of silent intervals. The ringing to
silent pattern is called the ringing cadence. During the silent
portion of ringing, the device can be programmed to any
other operating mode. The most likely candidates are low
power standby or forward active. Depending on system
requirements, the low or high battery may be selected.
Loop supervision is provided with the ring trip detector. The
ring trip detector senses the change in loop current when the
phone is taken off hook. The loop detector full wave rectifies
the ringing current, which is then filtered with external
components RRT and CRT. The resistor RRT sets the trip
threshold and the capacitor CRT sets the trip response time.
Most applications will require a trip response time less than
150 milliseconds.
Three very distinct actions occur when the devices detects a
ring trip. First, the DET output is latched low. The latching
mechanism eliminates the need for software filtering of the
detector output. The latch is cleared when the operating
mode is changed externally. Second, the VRS input is
disabled, removing the Tip biasing signal from the line. Third,
the device is internally forced to the forward active mode.
Power Dissipation
The power dissipation during ringing is dictated by the load
driving requirements and the ringing waveform. The key to
valid power calculations is the correct definition of average
and rms currents. The average current defines the high
battery supply current. The rms current defines the load
current.
The cadence provides a time averaging reduction in the
peak power. The total power dissipation consists of ringing
power, P_r, and the silent interval power, P_s.
P_RNG= P_r ⋅ -_t-_r----+^t--^r---_t-_s- + P_s ⋅ _t--_r----^t_+-^s----_t-_s-
(EQ. 32)
The terms, tr and ts, represent the cadence. The ringing
interval is tr and the silent interval is ts. The typical cadence
ratio tr:ts is 1:2.
The quiescent power of the device in the ringing mode is
defined in Equation 34.
P_r(Q)= VBH ⋅ IBH_Q + VBL ⋅ IBL_Q + VCC ⋅ ICC_Q
(EQ. 33)
During ringing, the device is operated from the low battery,
therefore the VBH power contribution is negligible. The total
power during the ringing interval is the sum of the quiescent
power and loading power:
P_r= P_r(Q) + VBL ⋅ I_AVG – -_Z---_R-----_E---_N---^V---+-^r2--^m--_R---^s-_L----_O----_O-----_P-
(EQ. 34)
For sinusoidal waveforms, the average current, I_AVG, is
defined in equation 36.
I_AVG=


2_{π--}
Z^----_R^----V-_E^----_Nr^{--m---+-s----}R^-⋅---_L^----_O^-2---_O^-----_P^-
(EQ. 35)
The only amplifier providing load current during ringing is the
Tip amplifier. Therefore the total power contribution from the
device is half the average power required by the load.
I_AVG=


1_{π--}
Z^----_R^----V-_E^----_Nr^{--m---+-s----}R^-⋅---_L^----_O^-2---_O^-----_P^-
(EQ. 36)
The silent interval power dissipation will be determined by
the quiescent power of the selected operating mode.
Power Denial
Overview
The power denial mode (111) will shutdown the entire device
except for the logic interface. Loop supervision is not
provided. This mode may be used as a sleep mode or to
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FN4539.3