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X40420_06 Datasheet, PDF (1/25 Pages) Intersil Corporation – Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch | |||
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PRELIMINARY
Data Sheet
X40420, X40421
4kbit EEPROM
May 25, 2006
FN8117.1
Dual Voltage Monitor with Integrated CPU
Supervisor and System Battery Switch
FEATURES
⢠Dual voltage detection and reset assertion
âThree standard reset threshold settings
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
âVTRIP2 programmable down to 0.9V
âAdjust low voltage reset threshold voltages
using special programming sequence
âReset signal valid to VCC = 1V
âMonitor two voltages or detect power fail
⢠Battery switch backup
⢠VOUT: 5mA to 50mA from VCC; or 250µA from
VBATT
⢠Fault detection register
⢠Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
⢠Selectable watchdog timer interval
(25ms, 200ms, 1.4s, off)
⢠Debounced manual reset input
⢠Low power CMOS
â25µA typical standby current, watchdog on
â6µA typical standby current, watchdog off
â1µA typical battery current in backup mode
⢠4Kbits of EEPROM
â16 byte page write mode
âSelf-timed write cycle
â5ms write cycle time (typical)
⢠Built-in inadvertent write protection
âPower-up/power-down protection circuitry
âBlock lock protect 0 or 1/2, of EEPROM
⢠400kHz 2-wire interface
⢠2.7V to 5.5V power supply operation
⢠Available packages
â14 Ld SOIC, TSSOP
⢠Pb-free plus anneal available (RoHS compliant)
⢠Monitor voltages: 5V to 1.6V
⢠Memory security
⢠Battery switch backup
⢠VOUT 5mA to 50mA
APPLICATIONS
⢠Communications equipment
âRouters, hubs, switches
âDisk arrays
⢠Industrial systems
âProcess control
âIntelligent instrumentation
⢠Computer systems
âDesktop computers
âNetwork servers
X40420, X40421
Standard VTRIP1 Level Standard VTRIP2 Level
4.6V (±1%)
2.9V(±1.7%)
4.6V (±1%)
2.6V (±2%)
2.9V(±1.7%)
1.6V (±3%)
See âOrdering Informationâ for more details
For Custom Settings, call Intersil.
Suffix
-A
-B
-C
DESCRIPTION
The X40420, X40421 combines power-on reset con-
trol, watchdog timer, supply voltage supervision, and
secondary supervision, manual reset, and Block
Lock⢠protect serial EEPROM in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to VCC activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
BLOCK DIAGRAM
V2MON
V2 Monitor
Logic
VOUT
+
VTRIP2
-
V2FAIL
SDA
WP
SCL
VCC
(V1MON)
BATT-ON
VOUT
VBATT
Data
Register
Command
Decode Test
& Control
Logic
System
Battery
Switch
Fault Detection
Register
Status
Register
EEPROM
Array
VCCLMogoicnitor
VOUT
+
VTRIP1
-
Watchdog
and
Reset Logic
VOUT
Power-on,
Manual Reset
Low Voltage
Reset
Generation
WDO
MR
RESET
X40420
RESET
X40421
LOWLINE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
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