HI3197 Datasheet, PDF (1/25 Pages) Intersil Corporation – 10-Bit, 125 MSPS D/A Converter

Data Sheet
HI3197
October 1998 File Number 4356.1
10-Bit, 125 MSPS D/A Converter
The HI3197 is a high-speed D/A converter which can
perform the multiplexed input of the two system 10-bit data.
The maximum conversion rate achieves 125 MSPS. The
multiplexed operation is possible by the 1/2 frequency-
divided clock or by halving the frequency of the clock with
the clock frequency divider circuit having the reset pin in
the IC. The data input is TTL; the clock input pin and reset
input pin can select either TTL or PECL according to the
application.
Ordering Information
PART NUMBER
HI3197JCQ
TEMP.
RANGE (^oC) PACKAGE
-20 to 75 48 Ld MQFP/
PQFP
PKG. NO.
Q48.7x7-S
Features
• Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bits
• Conversion Rate
125 MSPS (PECL)
100 MSPS (TTL)
• Data Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TTL
• Low Power Consumption . . . . . . . . . . . . . . . 400mW (Typ)
• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . 1.5pV•s
• Clock, Reset Input Level: TTL and PECL Compatible 2:1
Multiplexed Input Function
• ¹/₂ Frequency-Divided Clock Output Possible by the Built-
In Clock Frequency Divider Circuit
• Voltage Output (50Ω Load Drive Possible)
• Single Power Supply or ±Dual Power Supplies
• Polarity Switching Function of Reset Signal
Applications
• LCD
• DDS
• HDTV
• Communications (QPSK, QAM)
Pinout
HI3197 (MQFP)
TOP VIEW
AGND2
VOCLP
R POLARITY
INV
PS
DV_CC1
NC
DGND1
(MSB) DA9
DA8
DA7
DA6
36 35 34 33 32 31 30 29 28 27 26 25
37
24
38
23
39
22
40
21
41
20
42
19
43
18
44
17
45
16
46
15
47
14
48
13
1 2 3 4 5 6 7 8 9 10 11 12
RESETN/E
RESETP/E
RESET/T
CLKN/E
CLKP/E
CLK/T
DIV2OUT
DIV2IN
DB0 (LSB)
DB1
DB2
DB3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999