HCTS574MS Datasheet, PDF (1/11 Pages) Intersil Corporation – Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered

HCTS574MS
August 1995
Radiation Hardened Octal D-Type
Flip-Flop, Three-State, Positive Edge Triggered
Features
Pinouts
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm²/mg
• Single Event Upset (SEU) Immunity < 2 x 10^-9 Errors/Bit-
Day (Typ)
• Dose Rate Survivability: >1 x 10¹² RAD (Si)/s
• Dose Rate Upset >10¹⁰ RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
- Bus Driver O11utputs - 15 LSTTL Loads
• Military Temperature Range: -55^oC to +125^oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
20 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T20
TOP VIEW
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 CP
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
20 LEAD CERAMIC METAL SEAL
Description
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F20
The Intersil HCTS574MS is a Radiation Hardened non-inverting
TOP VIEW
octal D-type, positive edge triggered flip-flop with three-stateable
outputs. The HCTS574MS utilizes advanced CMOS/SOS ^OE
technology. The eight flip-flops enter data into their registers on ^D0
the LOW-to-HIGH transition of the clock (CP). Data is also ^D1
transferred to the outputs during this transition. The output ^D2
1
20
2
19
3
18
4
17
VCC
Q0
Q1
Q2
enable (OE) controls the three-state outputs and is independent ^Q3
5
16
Q3
of the register operation. When the output enable is high, the ^Q4
6
15
Q4
outputs are in the high impedance state.
D5
7
14
Q5
D6
The HCTS574MS utilizes advanced CMOS/SOS technology to
Q7
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
GND
8
13
Q6
9
12
Q7
10
11
CP
The HCTS574MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBER
HCTS574DMSR
HCTS574KMSR
HCTS574D/Sample
HCTS574K/Sample
HCTS574HMSR
TEMPERATURE RANGE
-55^oC to +125^oC
-55^oC to +125^oC
+25^oC
+25^oC
+25^oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
694
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
Spec Number 518629
File Number 2359.2