HCTS373MS Datasheet, PDF (1/11 Pages) Intersil Corporation – Radiation Hardened Octal Transparent Latch, Three-State

HCTS373MS
August 1995
Radiation Hardened
Octal Transparent Latch, Three-State
Features
Pinouts
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm²/mg
• Single Event Upset (SEU) Immunity < 2 x 10^-9 Errors/Bit-
Day (Typ)
• Dose Rate Survivability: >1 x 10¹² RAD (Si)/s
• Dose Rate Upset >10¹⁰ RAD (Si)/s 20ns Pulse
20 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T20
TOP VIEW
OE 1
Q0 2
D0 3
D1 4
20 VCC
19 Q7
18 D7
17 D6
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
• Military Temperature Range: -55^oC to +125^oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
20 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
Description
MIL-STD-1835 CDFP4-F20
TOP VIEW
The Intersil HCTS373MS is a Radiation Hardened octal transpar-
ent three-state latch with an active-low output enable. The out- ^OE
1
20
VCC
puts are transparent to the inputs when the Latch Enable (LE) is ^Q0
2
19
Q7
HIGH. When the Latch Enable (LE) goes LOW, the data is ^D0
3
18
D7
latched. The Output Enable (OE) controls the three-state outputs. ^D1
4
17
D6
When the Output Enable (OE) is HIGH, the outputs are in the Q1
5
16
Q6
high impedance state. The latch operation is independent of the Q2
6
15
Q5
state of the Output Enable.
D2
7
14
D5
The HCTS373MS utilizes advanced CMOS/SOS technology to
D3
achieve high-speed operation. This device is a member of ^Q3
radiation hardened, high-speed, CMOS/SOS Logic Family.
GND
8
13
D4
9
12
Q4
10
11
LE
The HCTS373MS is supplied in a 20 lead Ceramic flatpack (K
suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBER
HCTS373DMSR
HCTS373KMSR
HCTS373D/Sample
HCTS373K/Sample
HCTS373HMSR
TEMPERATURE RANGE
-55^oC to +125^oC
-55^oC to +125^oC
+25^oC
+25^oC
+25^oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
638
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
Spec Number 518636
File Number 2131.2