HCS132MS Datasheet, PDF (1/8 Pages) Intersil Corporation – Radiation Hardened Quad 2-Input NAND Schmitt Trigger

HCS132MS
August 1995
Radiation Hardened
Quad 2-Input NAND Schmitt Trigger
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm²/mg
• Single Event Upset (SEU) Immunity < 2 x 10^-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 10¹² RAD (Si)/s
• Dose Rate Upset >10¹⁰ RAD (Si)/s 20ns Pulse
• Cosmic Ray Upset Immunity < 2 x 10^-9 Errors/Gate Day (Typ
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55^oC to +125^oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
A1
Description
B1
The Intersil HCS132MS is a Radiation Hardened Quad 2-Input
Y1
NAND Schmitt Trigger inputs. A high on both inputs forces the
A2
output to a Low state.
B2
The HCS132MS utilizes advanced CMOS/SOS technology to
Y2
achieve high-speed operation. This device is a member of ^GND
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS132MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14
TOP VIEW
A1 1
B1 2
Y1 3
A2 4
B2 5
Y2 6
GND 7
14 VCC
13 B4
12 A4
11 Y4
10 B3
9 A3
8 Y3
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14
TOP VIEW
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
B4
A4
Y4
B3
A3
Y3
TRUTH TABLE
INPUTS
OUTPUTS
Ordering Information
An
Bn
Yn
L
L
H
PART
NUMBER
TEMPERATURE SCREENING
RANGE
LEVEL
PACKAGE
HCS132DMSR -55^oC to +125^oC Intersil Class 14 Lead SBDIP
S Equivalent
HCS132KMSR -55^oC to +125^oC Intersil Class 14 Lead Ceramic
S Equivalent Flatpack
HCS132D/
Sample
+25^oC
Sample
14 Lead SBDIP
HCS132K/
Sample
+25^oC
Sample
14 Lead Ceramic
Flatpack
HCS132HMSR
+25^oC
Die
Die
L
H
H
H
L
H
H
H
L
NOTE: L = Logic Level Low, H = Logic level High
Functional Diagram
nA
(1, 4, 9, 12)
nO
(2, 5, 10, 13)
nY
(3, 6, 8, 11)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
133
Spec Number 518750
File Number 3061.1