HCS11MS Datasheet, PDF (1/6 Pages) Intersil Corporation – Radiation Hardened Triple 3-Input AND Gate

HCS11MS
November 1994
Radiation Hardened
Triple 3-Input AND Gate
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K or 1 Mega-RAD(Si)
• Dose Rate Upset >10¹⁰ RAD(Si)/s 20ns Pulse
• Cosmic Ray Upset Immunity < 2 x 10^-9 Errors/Gate Day
(Typ)
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55^oC to +125^oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
14 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C
TOP VIEW
A1 1
B1 2
A2 3
B2 4
C2 5
Y2 6
GND 7
14 VCC
13 C1
12 Y1
11 C3
10 B3
9 A3
8 Y3
Description
The Intersil HCS11MS is a Radiation Hardened Triple 3-
Input AND Gate. A high on all inputs forces the output to a
High state.
The HCS11MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS11MS is supplied in a 14 lead Weld Seal Ceramic
flatpack (K suffix) or a Weld Seal Ceramic Dual-In-Line
Package (D suffix).
14 PIN CERAMIC FLAT PACK
MIL-STD-1835 DESIGNATOR CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
A2
B2
C2
Y2
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
C1
Y1
C3
B3
A3
Y3
Truth Table
INPUTS
OUTPUTS
An
Bn
Cn
Yn
L
L
L
L
L
L
H
L
L
H
L
L
L
H
H
L
H
L
L
L
H
L
H
L
H
H
L
L
H
H
H
H
NOTE: L = Logic Level Low, H = Logic level High
Functional Diagram
(1, 3, 9)
An
(2, 4, 10)
Bn
(13, 5, 11)
Cn
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-135
(12, 6, 8)
Yn
File Number 3048