CD4094BMS Datasheet, PDF (1/11 Pages) Intersil Corporation – CMOS 8-Stage Shift-and-Store Bus Register

CD4094BMS
December 1992
CMOS 8-Stage Shift-and-Store
Bus Register
Features
Pinout
• High Voltage Type (20V Rating)
• 3-State Parallel Outputs for Connection to Common
Bus
• Separate Serial Outputs Synchronous to Both Positive
and Negative Clock Edges for Cascading
• Medium Speed Operation - 5MHz at 10V (typ)
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25^oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
CD4094BMS
TOP VIEW
STROBE 1
DATA 2
CLOCK 3
Q1 4
Q2 5
Q3 6
Q4 7
VSS 8
16 VDD
15 OUTPUT ENABLE
14 Q5
13 Q6
12 Q7
11 Q8
10 Q’S
9 QS
Functional Diagram
Applications
• Serial-to-Parallel Data Conversion
• Remote Control Holding Register
• Dual-Rank Shift, Hold, and Bus Applications
SERIAL
OUTPUTS
DATA
2
10 Q’S
8-STAGE
CLOCK 3
SHIFT
9 QS
REGISTER
Description
CD4094BMS is a 8-stage serial shift register having a storage
latch associated with each stage for strobing data from the serial
input to parallel buffered 3-state outputs. The parallel outputs
may be connected directly to common bus lines. Data is shifted
on positive clock transitions. The data in each shift register stage
is transferred to the storage register when the STROBE input is
high. Data in the storage register appears at the outputs when-
ever the OUTPUT-ENABLE signal is high.
Two serial outputs are available for cascading a number of
CD4094BMS devices. Data is available at the QS serial output
terminal on positive clock edges to allow for high-speed opera-
tion in cascaded systems in which the clock rise time is fast. The
same serial information, available at the Q’S terminal on the next
negative clock edge, provides a means for cascading
CD4094BMS devices when the clock rise time is slow.
The CD4094BMS is supplied in these 16 lead outline packages:
STROBE 1
8-BIT
STORAGE
REGISTER
OUTPUT
ENABLE 15
3-STATE
OUTPUTS
VDD = 16
VSS = 8
PARALLEL OUTPUTS Q1 - Q8
(TERMINALS 4, 5, 6, 7, 14, 13, 12, 11, RESPECTIVELY)
Braze Seal DIP H4X
Frit Seal DIP
H1F
Ceramic Flatpack H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1083
File Number 3194