CD4076BMS Datasheet, PDF (1/9 Pages) Intersil Corporation – CMOS 4 -Bit D-Type Registers

CD4076BMS
December 1992
CMOS 4 -Bit D-Type Registers
Features
Pinout
• High Voltage Type (20V Rating)
• Three State Outputs
• Input Disabled Without Gating the Clock
• Gated Output Control Lines for Enabling or Disabling
the Outputs
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25^oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Description
CD4076BMS types are four-bit registers consisting of D-type
flip-flops that feature three-state outputs. Data Disable inputs
are provided to control the entry of data into the flip-flops.
When both Data Disable inputs are low, data at the D inputs
are loaded into their respective flip-flops on the next positive
transition of the clock input. Output Disable inputs are also
provided. When the Output Disable inputs are both low, the
normal logic states of the four outputs are available to the
load. The outputs are disabled independently of the clock by
a high logic level at either Output Disable input, and present
a high impedance.
The CD4076BMS is supplied in these 16 lead outline pack-
ages:
CD4076BMS
TOP VIEW
OUTPUT
DISABLE
M1
N2
Q1 3
Q2 4
Q3 5
Q4 6
CLOCK 7
VSS 8
16 VDD
15 RESET
14 DATA 1
13 DATA 2
12 DATA 3
11 DATA 4
10 G2 DATA
INPUT
9 G1 DISABLE
Functional Diagram
DATA INPUT
DISABLE
G1 G2
9 10
14
D1
13
D2
12
D3
11
D4
CLOCK
7
4D - TYPE
FLIP-FLOPS
WITH
AND-OR
LOGIC
15
RESET
OUTPUT
DISABLE
M
N
1
2
3
Q1
4
Q2
5
Q3
6
Q4
VSS = 8
VDD = 16
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H1E
H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1029
File Number 3325