CD4068BMS Datasheet, PDF (1/8 Pages) Intersil Corporation – CMOS 8 Input NAND/AND Gate

CD4068BMS
December 1992
CMOS 8 Input NAND/AND Gate
Features
• High Voltage Type (20V Rating)
• Medium Speed Operation
- TPHL, TPLH = 75ns (Typ.) at VDD = 10V
• Buffered Inputs and Outputs
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25^oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Description
CD4068BMS NAND/AND gate provides the system designer
with direct implementation of the positive logic 8 Input NAND and
AND functions and supplements the existing family of CMOS
gates.
The CD4068BMS is supplied in these 14 lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4H
H1B
H3W
Pinout
CD4068BMS
TOP VIEW
K=A·B·C·D·E·F·G·H 1
A2
B3
C4
D5
NC 6
VSS 7
14 VDD
13 J = A · B · C · D · E · F · G · H
12 H
11 G
10 F
9E
8 NC
NC = NO CONNECTION
Functional Diagram
2
A
3
B4
C
5
D
9
E
F ¹⁰
11
G
12
H
1
K
13
J
J=A·B·C·D·E·F·G·H
K=A·B·C·D·E·F·G·H
VDD = 14
VSS = 7
6, 8 = NO CONNECTION
Logic Diagram
A2
B3
C4
D5
E9
F 10
G 11
H 12
FIGURE 1. LOGIC DIAGRAM
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
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