CA3306 Datasheet, PDF (1/16 Pages) Intersil Corporation – 6-Bit, 15 MSPS, Flash A/D Converters

August 1997
CA3306, CA3306A,
CA3306C
6-Bit, 15 MSPS,
Flash A/D Converters
Features
Description
• CMOS Low Power with Video Speed (Typ) . . . . .70mW
• Parallel Conversion Technique
• Signal Power Supply Voltage . . . . . . . . . . . . 3V to 7.5V
• 15MHz Sampling Rate with Single 5V Supply
• 6-Bit Latched Three-State Output with Overflow Bit
• Pin-for-Pin Retrofit for the CA3300
Applications
• TV Video Digitizing
• Ultrasound Signature Analysis
• Transient Signal Analysis
• High Energy Physics Research
• High Speed Oscilloscope Storage/Display
• General Purpose Hybrid ADCs
• Optical Character Recognition
• Radar Pulse Analysis
• Motion Signature Analysis
• Robot Vision
The CA3306 family are CMOS parallel (FLASH) analog-to-digital
converters designed for applications demanding both low power
consumption and high speed digitization. Digitizing at 15MHz, for
example, requires only about 50mW.
The CA3306 family operates over a wide, full scale signal input volt-
age range of 1V up to the supply voltage. Power consumption is as
low as 15mW, depending upon the clock frequency selected. The
CA3306 types may be directly retrofitted into CA3300 sockets, offer-
ing improved linearity at a lower reference voltage and high operat-
ing speed with a 5V supply.
The intrinsic high conversion rate makes the CA3306 types ideally
suited for digitizing high speed signals. The overflow bit makes pos-
sible the connection of two or more CA3306s in series to increase
the resolution of the conversion system. A series connection of two
CA3306s may be used to produce a 7-bit high speed converter.
Operation of two CA3306s in parallel doubles the conversion speed
(i.e., increases the sampling rate from 15MHz to 30MHz).
Sixty-four paralleled auto balanced comparators measure the input
voltage with respect to a known reference to produce the parallel bit
outputs in the CA3306. Sixty-three comparators are required to
quantize all input voltage levels in this 6-bit converter, and the addi-
tional comparator is required for the overflow bit.
Ordering Information
PART NUMBER LINEARITY (INL, DNL)
CA3306E
±0.5 LSB
CA3306CE
±0.5 LSB
CA3306M
±0.5 LSB
CA3306CM
±0.5 LSB
CA3306D
±0.5 LSB
CA3306CD
±0.5 LSB
CA3306J3
±0.5 LSB
CA3306J3
±0.5 LSB
Pinouts
CA3306 (PDIP, SBDIP)
TOP VIEW
SAMPLING RATE
15MHz (67ns)
10MHz (100ns)
15MHz (67ns)
10MHz (100ns)
15MHz (67ns)
10MHz (100ns)
15MHz (67ns)
10MHz (100ns)
TEMP. RANGE (^oC)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
18 Ld PDIP
18 Ld PDIP
20 Ld SOIC
20 Ld SOIC
18 Ld SBDIP
18 Ld SBDIP
20 Ld CLCC
20 Ld CLCC
PKG. NO.
E18.3
E18.3
M20.3
M20.3
D18.3
D18.3
J20.B
J20.B
CA3306 (SOIC)
TOP VIEW
CA3306 (CLCC)
TOP VIEW
(MSB) B6 1
OVERFLOW 2
V_SS 3
V_Z 4
CE2 5
CE2 6
CLK 7
PHASE 8
V_REF+ 9
18 B5
17 B4
16
REF
CENTER
15 B3
14 B2
13 B1 (LSB)
12 V_DD
11 V_IN
10 V_REF-
(MSB) B6 1
OVERFLOW 2
V_SS 3
NC 4
V_Z 5
CE2 6
CE1 7
CLK 8
PHASE 9
V_REF+ 10
20 B5
19 B4
18
REF
CENTER
17 B3
16 B2
15 B1 (LSB)
14 V_DD
13 NC
12 V_IN
11 V_REF-
3 2 1 20 19
V_SS 4
V_Z 5
18
REF
CENTER
17 B3
NC 6
16 B2
CE2 7
15 B1 (LSB)
CE1 8
14 V_DD
9 10 11 12 13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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4-8
File Number 3102.1