865G Datasheet, PDF (92/249 Pages) Intel Corporation – Intel 865G/865GV Graphics and Memory Controller Hub

Register Description
3.6.11
3.6.12
3.6.13
SBUSN1—Secondary Bus Number Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
19h
00h
R/W
8 bits
This register identifies the bus number assigned to the second bus side of the virtual PCI-to-PCI
bridge (i.e., to PCI_B/AGP). This number is programmed by the PCI configuration software to
allow mapping of configuration cycles to PCI_B/AGP.
Bit
Descriptions
7:0
Secondary Bus Number (SBUSN)—RO. This field is programmed by configuration software with
the bus number assigned to PCI_B.
SUBUSN1—Subordinate Bus Number Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
1Ah
00h
R/W
8 bits
This register identifies the subordinate bus (if any) that resides at the level below PCI_B/AGP. This
number is programmed by the PCI configuration software to allow mapping of configuration
cycles to PCI_B/AGP.
Bit
Descriptions
Subordinate Bus Number (BUSN)—R/W. This register is programmed by configuration software
7:0
with the number of the highest subordinate bus that lies behind the Device 1 bridge. When only a
single PCI device resides on the AGP/PCI_B segment, this register will contain the same value as
the SBUSN1 register.
SMLT1—Secondary Bus Master Latency Timer Register
(Device 1)
Address Offset:
Default Value:
Access:
Size:
1Bh
00h
RO, R/W
8 bits
This register control the bus tenure of the GMCH on AGP/PCI the same way Device 0 MLT
controls the access to the PCI_A bus.
Bit
Descriptions
7:3 Secondary MLT Counter Value (MLT)—R/W. Programmable, default = 0 (SMLT disabled)
2:0 Reserved.
Intel^® 82865G/82865GV GMCH Datasheet
93