865G Datasheet, PDF (132/249 Pages) Intel Corporation – Intel 865G/865GV Graphics and Memory Controller Hub

Register Description
The remaining 7 bits of each of these registers are compared against address lines 31:26 to
determine which row is being addressed by the current cycle. In either of the dual-channel modes,
the GMCH supports a total of 4 rows of memory (only DRB0:3 are used). When in either of the
dual-channel modes and four rows populated with 512-Mb technology, x8 devices, the largest
memory size of 4 GB is supported. In this case, DRB3 is programmed to 40h. In the dual-channel
modes, DRB[7:4] must be programmed to the same value as DRB3. In single-channel mode, all
eight DRB registers are used. In this case, DRB[3:0] are used for the rows in channel A and
DRB[7:4] are used for rows populated in channel B. If only channel A is populated, then only
DRB[3:0] are used. DRB[7:4] are programmed to the same value as DBR3. If only channel B is
populated, then DRB[7:4] are used and DRB[3:0] are programmed to 00h. When both channels are
populated but not identically, all of the DRB registers are used. This configuration is referred to as
“virtual single-channel mode.”
Row0: 0000h
Row1: 0001h
Row2: 0002h
Row3: 0003h
Row4: 0004h
Row5: 0005h
Row6: 0006h
Row7: 0007h
0008h, reserved
0009h, reserved
000Ah, reserved
000Bh, reserved
000Ch, reserved
000Dh, reserved
000Eh, reserved
000Fh, reserved
DRB0 = Total memory in Row0 (in 64-MB increments)
DRB1 = Total memory in Row0 + Row1 (in 64-MB increments)
DRB2 = Total memory in Row0 + Row1 + Row2 (in 64-MB increments)
DRB3 = Total memory in Row0 + Row1 + Row2 + Row3 (in 64-MB increments)
DRB4 = Total memory in Row0 + Row1 + Row2 + Row3 + Row4 (in 64-MB increments)
DRB5 = Total memory in Row0 + Row1 + Row2 + Row3 + Row4 + Row5 (in 64-MB increments)
DRB6 = Total memory in Row0 + Row1 + Row2 + Row3 + Row4 + Row5 + Row6
(in 64-MB increments)
DRB7 = Total memory in Row0 + Row1 + Row2 + Row3 + Row4 + Row5 + Row6 + Row7
(in 64-MB increments)
Each row is represented by a byte. Each byte has the following format:
Bit
Description
7 Reserved.
DRAM Row Boundary Address—R/W. This 7-bit value defines the upper and lower addresses for
6:0
each SDRAM row. This 7-bit value is compared against address lines 0,31:26 (0 concatenated with
the address bits 31:26) to determine which row the incoming address is directed.
Default= 0000001b
Intel^® 82865G/82865GV GMCH Datasheet
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