80C31BH Datasheet, PDF (8/16 Pages) Intel Corporation – CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

AUTOMOTIVE 80C31BH 80C51BH 87C51
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias ^b40 C to ^a125 C
Storage Temperature
b_{65 C to} a_{150 C}
Voltage on EA V_PP Pin to V_SS
0V to ^a13 0V
Voltage on Any Other Pin to V_SS ^b0 5V to ^a6 5V
I_OL per I O pin
15 mA
Power Dissipation
1 5W
(Based on package heat transfer limitations not de-
vice power consumption)
Typical Junction Temperature (T_J)
a_{135 C}
(Based upon ambient temperature at ^a125 C)
Typical Thermal Resistance Junction-to-Ambient
(i_JA)
PDIP
75 C W
PLCC
46 C W
NOTICE This is a production data sheet The specifi-
cations are subject to change without notice
WARNING Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage
These are stress ratings only Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability
DC CHARACTERISTICS
(T_A ^{e b}40 C to ^a125 C V_CC ^e 5V g10% (5V g20% EPROM Only) V_SS ^e 0V)
Symbol
Parameter
Min
Typ(1)
Max
(87C51 80C51BH)
Unit
Test
Conditions
V_IL
V_IL1
V_IH
V_IH1
V_OL
V_OL1
V_OH
V_OH1
I_IL
I_TL
Input Low Voltage (Except EA)
b0 5
Input Low Voltage to EA
0
Input High Voltage (Except XTAL1 RST) 0 2V_CCa1 0
Input High Voltage (XTAL1 RST)
0 7 V_CCa0 1
Output Low Voltage (Ports 1 2 3)
Output Low Voltage (Port 0 ALE PSEN)
Output High Voltage
(Ports 1 2 3 ALE PSEN)
Output High Voltage (Port 0 in
External Bus Mode)
Logical 0 Input Current (Ports 1 2 3)
24
0 9 V_CC
24
0 9 V_CC
Logical 1-to-0 transition current
(Ports 1 2 3)
0 2 V_CCb0 25
0 2 V_CCb0 45
V_CCa0 5
V_CCa0 5
0 45⁽⁷⁾
0 45⁽⁷⁾
b75
b750
V
V
V
V
V I_OL e 1 6 mA⁽²⁾
V I_OL e 3 2 mA⁽²⁾
V I_OH e b60 mA
V I_OH e b10 mA
V I_OH e b800 mA
V I_OH e b80 mA⁽³⁾
mA V_IN e 0 45 V
mA
(4)
I_LI
I_CC
RRST
Input Leakage Current (Port 0)
Power Supply Current
Active Mode 12 MHz ⁽⁵⁾
Idle Mode 12 MHz ⁽⁵⁾
Power Down Mode
Internal Reset Pulldown Resistor
11 5
13
3
50
g10
25 20
65
100 75
300
mA V_IN e V_IL or V_IH
mA
mA
(6)
mA V_CC e 2 2V to 5 5V
KX
CIO
Pin Capacitance
10
pF
NOTES
1 ‘‘Typicals’’ are based on a limited number of samples taken from early manufacturing lots and are not guaranteed The
values listed are at room temp 5V
2 Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V_OLs of ALE and Ports
1 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-
to-0 transitions during bus operations In the worst cases (capacitive loading ^l 100pF) the noise pulse on the ALE pin may
exceed 0 8V In such cases it may be desirable to qualify ALE with a Schmitt Trigger or use an address latch with a Schmitt
Trigger STROBE input
3 Capacitive loading on Ports 0 and 2 may cause the V_OH on ALE and PSEN to momentarily fall below the 0 9 V_CC
specification when the address bits are stabilizing
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