80C31BH Datasheet, PDF (5/16 Pages) Intel Corporation – CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

AUTOMOTIVE 80C31BH 80C51BH 87C51
Port 3 also serves the functions of various special
features of the MCS 51 microcontroller family as
listed below
Pin Name
Alternate Function
P3 0
P3 1
P3 2
P3 3
P3 4
P3 5
P3 6
P3 7
RXD
TXD
INT0
INT1
T0
T1
WR
RD
Serial Input Line
Serial Output Line
External Interrupt 0
External Interrupt 1
Timer 0 External Input
Timer 1 External Input
External Data Memory Write Strobe
External Data Memory Read Strobe
Port 3 also receives some control signals for
EPROM programming and program verification
RESET Reset input A logic high on this pin for two
machine cycles while the oscillator is running resets
the device An internal pulldown resistor permits a
power-on reset to be generated using only an exter-
nal capacitor to V_CC
ALE PROG (EPROM Only) Address Latch Enable
output signal for latching the low byte of the address
during accesses to external memory This pin is also
the program pulse input (PROG) during EPROM pro-
gramming
In normal operation ALE is emitted at a constant
rate of 1 6 the oscillator frequency and may be
used for external timing or clocking purposes Note
however that one ALE pulse is skipped during each
access to external Data Memory
PSEN Program Store Enable is the Read strobe
to External Program Memory When the
87C51 80C51BH is executing from Internal Program
Memory PSEN is inactive (high) When the device is
executing code from External Program Memory
PSEN is activated twice each machine cycle except
that two PSEN activations are skipped during each
access to External Data Memory
EA V_PP External Access enable EA must be
strapped to V_SS in order to enable the
87C51 80C51BH to fetch code from External Pro-
gram Memory locations starting at 0000H up to
0FFFFH Note however that if either of the Lock
Bits is programmed the logic level at EA is internally
latched during reset (EPROM only )
EA must be strapped to V_CC for internal program
execution
V_PP (EPROM Only) This pin also receives the
12 75V programming supply voltage (V_PP) during
EPROM programming
270419 – 5
Figure 4 Using the On-Chip Oscillator
270419 – 6
Figure 5 External Clock Drive
XTAL1 Input to the inverting oscillator amplifier and
input to the internal clock generating circuits
XTAL2 Output from the inverting oscillator amplifi-
er
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output respec-
tively of an inverting amplifier which can be config-
ured for use as an on-chip oscillator as shown in
Figure 4
To drive the device from an external clock source
XTAL1 should be driven while XTAL2 is left uncon-
nected as shown in Figure 5 There are no require-
ments on the duty cycle of the external clock signal
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop but minimum and
maximum high and low times specified on the Data-
sheet must be observed
IDLE MODE
In Idle Mode the CPU puts itself to sleep while all
the on-chip peripherals remain active The mode is
invoked by software The content of the on-chip
RAM and all the Special Functions Registers remain
unchanged during this mode The Idle Mode can be
terminated by any enabled interrupt or by a hard-
ware reset
It should be noted that when Idle is terminated by a
hardware reset the device normally resumes pro-
gram execution from where it left off up to two ma-
chine cycles before the internal reset algorithm
takes control On-chip hardware inhibits access to
5