FW82801E Datasheet, PDF (79/84 Pages) Intel Corporation – Intel 82801E Communications I/O Controller Hub (C-ICH)

Intel^® 82801E C-ICH
Table 57. XOR Chain #1
(RTCRST# Asserted for four PCI Clocks while
PWROK Active)
Pin Name
Ball #
Notes
SIU0_RXD
SIU0_TXD
SIU0_CTS#
SIU0_DSR#
SIU0_DCD#
SIU0_RI#
SIU0_DTR#
SIU0_RTS#
SIU1_RXD
SIU1_TXD
SIU1_CTS#
SIU1_DSR#
SIU1_DCD#
SIU1_RI#
SIU1_DTR#
SIU1_RTS#
SIU_LDRQ#
SIU_LAD[3]
SIU_LFRAME#
SIU_LAD[0]
SIU_LAD[1]
SIU_LAD[2]
SIU_SERIRQ
SIU_RESET#
LFRAME#
/FWH4
FWH3
/LAD3
TP0
FWH0
/LAD0
FWH1
/LAD1
FWH2
/LAD2
THRM#
E17 Top of XOR Chain 1
D19
Second signal in
XOR
D17
D18
B20
A21
B19
E16
B18
C17
D16
A18
C16
D15
B16
A16
C15
E14
B15
D14
A15
C14
A14
D13
C13
B13
A12
B12
D12
E12
A11
Table 57. XOR Chain #1
(RTCRST# Asserted for four PCI Clocks while
PWROK Active)
Pin Name
Ball #
Notes
LDRQ0#
LDRQ1#
GPIO[21]
GNTA#
/GPIO16
REQB#
/REQ5#
/GPIO1
GNTB#
/GNT5#
/GPIO17
GNT1#
GNT0#
REQA#
/GPIO0
PIRQH#
PIRQG#
/GPIO4
PIRQF#
/GPIO3
PIRQE#
/GPIO2
PIRQD#
PIRQA#
PIRQB#
PIRQC#
REQ0#
REQ1#
REQ2#
GNT2#
GNT3#
AD_26
AD_30
AD_24
AD_28
TP[2]
B11
C11
A10
B10
C10
B9
D10
A8
C9
A7
E11
E10
C8
B7
A5
D8
C7
B5
D7
E9
E8
A3
B4
C5
D6
A2
AC2
XOR Chain #1
Output
Advance Information Datasheet
79