FW82801E Datasheet, PDF (62/84 Pages) Intel Corporation – Intel 82801E Communications I/O Controller Hub (C-ICH)

Intel^® 82801E C-ICH
4.4
AC Characteristics
Table 42. Clock Timings (Sheet 1 of 2)
Sym
Parameter
Min Max Unit Notes Figure
PCI Clock (PCICLK)
t1
Period
t2
High Time
30 33.3
ns
9
12
ns
9
t3
Low Time
t4
Rise Time
t5
Fall Time
12
ns
9
3
ns
9
3
ns
9
Oscillator Clock (OSC)
t6
Period
t7
High Time
t8
Low time
67
70
ns
9
20
9
20
ns
9
USB Clock (USBCLK)
fclk48
t9
t10
t11
t12
t13
Operating Frequency
Frequency Tolerance
High Time
Low time
Rise Time
Fall Time
48
MHz
500 ppm
1
7
ns
9
7
ns
9
1.2
ns
9
1.2
ns
9
Suspend Clock (SUSCLK)
fsusclk
t14
t15
Operating Frequency
High time
Low Time
32
10
10
KHz
4
µs
4
9
µs
4
9
SMBus Clock (SMBCLK)
fsmb
t18
t19
t20
t21
Operating Frequency
High time
Low time
Rise time
Fall time
10
16
KHz
4.0
50
µs
2
24
4.7
µs
24
1000
ns
24
300
ns
24
I/O APIC Clock (APICCLK)
fioap Operating Frequency
14.32 33.33 MHz
NOTES:
1. The USBCLK is a 48 MHz that expects a 40/60% duty cycle. The source of this PPM is external to this
component.
2. The maximum high time (t18 Max) provide a simple guaranteed method for devices to detect bus idle
conditions.
3. This specification includes pin-to-pin skew from the clock generator as well as board skew.
4. SUSCLK duty cycle can range from 30% minimum to 70% maximum.
62
Advance Information Datasheet