6700PXH Datasheet, PDF (57/194 Pages) Intel Corporation – 64-bit PCI Hub

Signal Description
Setting the base address to a value greater than that of the limit address turns off the I/O range.
When the I/O range is turned off, no I/O transactions are forwarded to the PCI bus even if the I/O
enable bit is set. The I/O range has a minimum granularity of 4 Kbytes and is aligned on a 4-Kbyte
boundary. The maximum I/O range is 64 Kbytes. This range may be lowered to 1 KB granularity
by setting the EN1K bit in the Intel® 6700PXH 64-bit PCI Hub Configuration Register at offset
40h.
The base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit field at
address 30h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O base address. The bottom
4 bits are read only; returning value 0h to indicate that the Intel® 6700PXH 64-bit PCI Hub
supports 16-bit I/O addressing. Bits [1:0] of the base address are assumed to be 0,which naturally
aligns the base address to a 4-Kbyte boundary. The I/O base upper 16 bits register at offset 30h is
Reserved. Reset initializes the value of the I/O base address to 0000h.
The I/O limit register consists of an 8-bit field at offset 1Dh and a16-bit field at offset 32h. The top
4 bits of the 8-bit field define bits [15:12] of the I/O limit address. The bottom 4 bits are read only,
returning value 0h to indicate that 16-bit I/O addressing is supported. Bits [11:0] of the limit
address are assumed to be FFFh, which naturally aligns the limit address to the top of a 4-Kbyte I/O
address block. The 16 bits contained in the I/O limit upper 16 bits register at offset 32h are
Reserved. Reset initializes the value of the I/O limit address to 0FFFh.
Note:
If the EN1K bit is set in the Intel® 6700PXH 64-bit PCI Hub Configuration Register, the Base and
Limit Registers are changed such that the top 6 bits of the 8-bit field define bits [15:10] of the I/O
base/limit address, and the bottom 2 bits read only as 0h to indicate support for 16-bit I/O
addressing. Bits [9:0] are assumed to be 0 (for the base register) and 1 (for the limit register), which
naturally aligns the address to a 1-Kbyte boundary.
2.13.2 Memory Window Addressing
2.13.2.1 Mode Memory Access
2.13.2.1.15 Memory Access from the PCI to the PCI Express* Bus
Two memory windows can be set up for forwarding memory transactions from the PCI Express* to
the PCI bus. These windows are defined as part of the standard bridge configuration space. Inverse
decoding is used for forwarding transactions from PCI to PCI Express*.
This section describes the memory windows that can be set up in the bridge. The register bits listed
below also modify the Intel® 6700PXH 64-bit PCI Hub response to memory transactions:
• Memory-mapped I/O Base and Limit Registers
• Prefetchable Memory Base and Limit Registers
• Prefetchable Memory Base and Limit Upper 32 bits Register
• Memory Enable bit in the Command Register
• Master Enable bit in the Command register
To enable outbound memory transactions, the Memory Space Enable bit (bit 1) in the PD_CMD
Register must be set (offset 04–05h). To enable inbound memory transactions, the Master Enable
bit (bit 2) in the PD_CMD Register must be set (offset 04–05h). The Intel® 6700PXH 64-bit PCI
Hub will not prefetch data from PCI devices. The Intel® 6700PXH 64-bit PCI Hub supports 64 bits
of addressing (DAC cycles) on both interfaces.
Intel® 6700PXH 64-bit PCI Hub Datasheet
57