6700PXH Datasheet, PDF (46/194 Pages) Intel Corporation – 64-bit PCI Hub

Signal Description
Table 2-21. Split Completion Abort Registers
Index
Message
00h
Master-Abort: The Intel® 6700PXH 64-bit PCI Hub encountered a Master-Abort on the destination
bus.
01h
Target-Abort: The Intel® 6700PXH 64-bit PCI Hub encountered a Target-Abort on the destination
bus.
2.11.7
LOCK Cycles
A lock is established when a memory read from the PCI Express* bus that targets a PCI bus agent
with the lock bit set is responded to with a PxTRDY# by a PCI target. The bus is unlocked when
the Unlock Special Cycle is sent on the PCI Express* interface. When the PCI bus is locked, all
inbound memory transactions from that bus are retried. The Intel® 6700PXH 64-bit PCI Hub
inbound read prefetch engine stops issuing any more requests on the PCI Express* bus. Note
though that read completions for inbound read requests issued ahead of the lock being established
on the PCI bus could return on the PCI Express* bus after the PCI lock has been established, and
the Intel® 6700PXH 64-bit PCI Hub accepts them.
Once the bus is locked, any PCI Express* cycle to PCI will be driven with the PxLOCK# pin
asserted, even if that particular cycle is not locked. This should not occur, because under lock, peer-
to-peer accesses will be internally blocked and the MCH should not be sending any non-locked
transactions downstream.
When one PCI bus segment is locked on the Intel® 6700PXH 64-bit PCI Hub, the other is still free
to accept cycles, i.e. that bus is not locked. However, these cycles are not allowed to proceed on the
PCI Express* bus or the locked PCI segment. Therefore, once the PCI bus is locked, no more
cycles will proceed onto the PCI Express* bus from the non-locked PCI segment, or from the
I/OxAPIC(s).
If during the LOCK sequence, any of the locked read commands results in a master or target abort
(either on the PCI bus or the internal switch interconnect), then the Intel® 6700PXH 64-bit PCI
Hub loses lock after sending a completion packet on the PCI Express* bus. In the case of a memory
write receiving a target or master abort during a LOCK sequence, the Intel® 6700PXH 64-bit PCI
Hub only unlocks after the unlock message is received on the PCI Express* bus. Outbound LOCK
is supported by the Intel® 6700PXH 64-bit PCI Hub.
Inbound LOCK transactions are treated with the LOCK signal ignored. Also locks to internal
devices, the SHPC, or the I/OxAPIC are not supported by the Intel® 6700PXH 64-bit PCI Hub.
See the summary in Table 2-22 for a summary of Intel® 6700PXH 64-bit PCI Hub responses to
LOCK transactions.
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Intel® 6700PXH 64-bit PCI Hub Datasheet