21152 Datasheet, PDF (46/148 Pages) Intel Corporation – PCI-to-PCI Bridge

PCI Bus Operation
4.6.2
Nonprefetchable Read Transactions
A nonprefetchable read transaction is a read transaction where the 21152 requests 1—and only
1—Dword from the target and disconnects the initiator after delivery of the first Dword of read
data. Unlike prefetchable read transactions, the 21152 forwards the read byte enable information
for the data phase.
Nonprefetchable behavior is used for I/O and configuration read transactions, as well as for
memory read transactions that fall into nonprefetchable memory space.
If extra read transactions could have side effects, for example, when accessing a FIFO, use
nonprefetchable read transactions to those locations. Accordingly, if it is important to retain the
value of the byte enable bits during the data phase, use nonprefetchable read transactions. If these
locations are mapped in memory space, use the memory read command and map the target into
nonprefetchable (memory-mapped I/O) memory space to utilize nonprefetching behavior.
4.6.3
Table 4.5
Read Prefetch Address Boundaries
The 21152 imposes internal read address boundaries on read prefetching. When a read transaction
reaches one of these aligned address boundaries, the 21152 stops prefetching data, unless the target
signals a target disconnect before the read prefetch boundary is reached. When the 21152 finishes
transferring this read data to the initiator, it returns a target disconnect with the last data transfer,
unless the initiator completes the transaction before all prefetched read data is delivered. Any
leftover prefetched data is discarded.
Prefetchable read transactions in flow-through mode prefetch to the nearest aligned 4KB address
boundary, or until the initiator deasserts FRAME#. Section 4.6.6 describes flow-through mode
during read operations.
Table 4.5 shows the read prefetch address boundaries for read transactions during
non-flow-through mode.
Read Prefetch Address Boundaries
Type of Transaction
Configuration read
I/O read
Memory read
Memory read
Memory read
Memory read line
Address Space
—
—
Nonprefetchable
Prefetchable
Prefetchable
—
Memory read line
—
Memory read multiple
—
Memory read multiple
—
Cache Line Size
—
—
—
CLS ≠ 1, 2, 4, 8
CLS = 1, 2, 4, 8
CLS ≠ 1, 2, 4, 8
CLS = 1, 2, 4, 8
CLS ≠ 1, 2, 4, 8
CLS = 1, 2, 4, 8
Prefetch Aligned
Address Boundary
1 Dword (no prefetch)
1 Dword (no prefetch)
1 Dword (no prefetch)
16-Dword aligned
address boundary
Cache line address
boundary
16-Dword aligned
address boundary
Cache line boundary
Queue full
Second cache line
boundary
4-12
21152 PCI-to-PCI Bridge Preliminary Datasheet