21152 Datasheet, PDF (35/148 Pages) Intel Corporation – PCI-to-PCI Bridge

PCI Bus Operation
4
This chapter presents detailed information about PCI transactions, transaction forwarding across
the 21152, and transaction termination.
4.1
Types of Transactions
Table 4-1.
This section provides a summary of PCI transactions performed by the 21152.
Table 4-1 lists the command code and name of each PCI transaction. The Master and Target
columns indicate 21152 support for each transaction when the 21152 initiates transactions as a
master, on the primary bus and on the secondary bus, and when the 21152 responds to transactions
as a target, on the primary bus and on the secondary bus.
21152 PCI Transactions
Type of Transaction
0000 Interrupt acknowledge
0001 Special cycle
0010 I/O read
0011 I/O write
0100 Reserved
0101 Reserved
0110 Memory read
0111 Memory write
1000 Reserved
1001 Reserved
1010 Configuration read
1011 Configuration write
1100 Memory read multiple
1101 Dual address cycle
1110 Memory read line
1111 Memory write and invalidate
21152 Initiates as Master
Primary
Secondary
No
No
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Yes
Yes
Yes
Yes
No
No
No
No
No
Yes
Type 1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
21152 Responds as Target
Primary
Secondary
No
No
No
No
Yes
Yes
Yes
Yes
No
No
No
No
Yes
Yes
Yes
Yes
No
No
No
No
Yes
No
Yes
Type 1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
As indicated in Table 4-1, the following PCI commands are not supported by the 21152:
• The 21152 never initiates a PCI transaction with a reserved command code and, as a target, the
21152 ignores reserved command codes.
• The 21152 never initiates an interrupt acknowledge transaction and, as a target, the 21152
ignores interrupt acknowledge transactions. Interrupt acknowledge transactions are expected
to reside entirely on the primary PCI bus closest to the host bridge.
• The 21152 does not respond to special cycle transactions and cannot guarantee delivery of a special
cycle transaction to downstream buses, due to the broadcast nature of the special cycle command,
and the inability to control the transaction as a target. To generate special cycle transactions on other
PCI buses, either upstream or downstream, a Type 1 configuration command must be used.
• The 21152 does not generate Type 0 configuration transactions on the primary interface, nor does
it respond to Type 0 configuration transactions on the secondary PCI interface. The PCI-to-PCI
Bridge Architecture Specification does not support configuration from the secondary bus.
21152 PCI-to-PCI Bridge Preliminary Datasheet
4-1