28F800C3 Datasheet, PDF (40/68 Pages) Intel Corporation – Advanced+ Boot Block Flash Memory (C3)

Intel^£ Advanced+ Boot Block Flash Memory (C3)
Table 14. Read Operations—16 Mbit Density
Density
16 Mbit
Para- ^Product
70 ns
80 ns
90 ns
110 ns
# Sym mete
Unit Notes
r
V_CC 2.7 V–3.6 V 2.7 V–3.6 V 3.0 V–3.6 V 2.7 V–3.6 V 3.0 V–3.6V 2.7 V–3.6V
Min Max Min Max Min Max Min Max Min Max Min Max
R1 t_AVAV Read Cycle Time 70
80
80
90
100
110
ns 3,4
R2
t_AVQ Address to
V ^{Output Delay}
70
80
80
90
100
110 ns 3,4
R3
t_ELQ CE# to Output
V ^Delay
70
80
80
90
100
110 ns 1,3,4
R4
t_GLQ OE# to Output
V ^Delay
20
20
30
30
30
30 ns 1,3,4
R5
t_PHQ RP# to Output
V ^Delay
150
150
150
150
150
150 ns 3,4
R6
t_ELQ CE# to Output in
X ^{Low Z}
0
0
0
0
0
0
ns 2,3,4
R7
t_GLQ OE# to Output in
X ^{Low Z}
0
0
0
0
0
0
ns 2,3,4
R8
t_EHQ CE# to Output in
Z ^{High Z}
20
20
20
20
20
20 ns 2,3,4
R9
t_GHQ OE# to Output in
Z ^{High Z}
20
20
20
20
20
20 ns 2,3,4
Output Hold from
Address, CE#, or
R10 t_OH OE# Change,
0
0
0
0
0
0
ns 2,3,4
Whichever
Occurs First
NOTES:
1. OE# may be delayed up to t_ELQV–t_GLQV after the falling edge of CE# without impact on t_ELQV.
2. Sampled, but not 100% tested.
3. See Figure 8, “Read Operation Waveform” on page 42.
4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 for timing measurements and maximum allowable input
slew rate.
40
Datasheet