28F016XS Datasheet, PDF (33/54 Pages) Intel Corporation – 16-MBIT (1 MBIT x 16, 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY

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28F016XS FLASH MEMORY
5.6 Timing Nomenclature
All 3.3V system timings are measured from where signals cross 1.5V.
For 5.0V systems, use the standard JEDEC cross point definitions (standard testing) or from where signals
cross 1.5V (high speed testing).
Each timing parameter consists of five characters. Some common examples are defined below:
t_ELCH time(t) from CE# (E) going low (L) to CLK (C) going high (H)
t_AVCH time(t) from address (A) valid (V) to CLK (C) going high (H)
t_WHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X)
Pin Characters
A
Address Inputs
H
High
Pin States
C
CLK (Clock)
D
Data Inputs
L
Low
V
Valid
Q
Data Outputs
E
CE# (Chip Enable)
F
BYTE# (Byte Enable)
X
Driven, but Not Necessarily Valid
Z
High Impedance
L
Latched
G
OE# (Output Enable)
W
WE# (Write Enable)
P
RP# (Deep Power-Down Pin)
R
RY/BY# (Ready Busy)
V
ADV# (Address Valid)
Y
3/5# Pin
5V
V_CC at 4.5V Minimum
3V
V_CC at 3.0V Minimum
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