28F016XS Datasheet, PDF (12/54 Pages) Intel Corporation – 16-MBIT (1 MBIT x 16, 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY

28F016XS FLASH MEMORY
E
2.1 Lead Descriptions
Symbol
Type
Name and Function
A0
INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when device is
in x8 mode. This address is latched in x8 data programs and ignored in x16
mode (i.e., the A₀ input buffer is turned off when BYTE# is high).
A1
INPUT BANK-SELECT ADDRESS: Selects an even or odd bank in a selected block.
A 128-Kbyte block is subdivided into an even and odd bank. A₁ = 0 selects the
even bank and A₁ = 1 selects the odd bank, in both byte-wide mode and word-
wide mode device configurations.
A₂–A16
INPUT
WORD-SELECT ADDRESSES: Select a word within one 128-Kbyte block.
Address A₁ and A7–16 select 1 of 2048 rows, and A2–6 select 16 of 512
columns. These addresses are latched during both data reads and programs.
A17–A20
INPUT BLOCK-SELECT ADDRESSES: Select 1 of 16 erase blocks. These
addresses are latched during data programs, erase and lock-block operations.
DQ0–DQ7
INPUT/
OUTPUT
LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.
Outputs array, identifier or status data in the appropriate read mode. Floated
when the chip is de-selected or the outputs are disabled.
DQ8–DQ15
CE₀#, CE₁#
RP#
OE#
INPUT/
OUTPUT
INPUT
INPUT
INPUT
HIGH-BYTE DATA BUS: Inputs data during x16 data program operations.
Outputs array or identifier data in the appropriate read mode; not used for
Status Register reads. Outputs floated when the chip is de-selected, the
outputs are disabled (OE# = V_IH) or BYTE# is driven active.
CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,
decoders and sense amplifiers. With either CE0# or CE1# high, the device is
de-selected and power consumption reduces to standby levels upon
completion of any current data program or erase operations. Both CE0# and
CE1# must be low to select the device.
All timing specifications are the same for both signals. Device Selection occurs
with the latter falling edge of CE0# or CE1#. The first rising edge of CE0# or
CE1# disables the device.
RESET/POWER-DOWN: RP# low places the device in a deep power-down
state. All circuits that consume static power, even those circuits enabled in
standby mode, are turned off. When returning from deep power-down, a
recovery time of tPHCH is required to allow these circuits to power-up.
When RP# goes low, the current WSM operation is terminated, and the device
is reset. All Status Registers return to ready, clearing all status flags. Exit from
deep power-down places the device in read array mode.
OUTPUT ENABLE: Drives device data through the output buffers when low.
The outputs float to tri-state off when OE# is high. CEx# overrides OE#, and
OE# overrides WE#.
WE#
INPUT
WRITE ENABLE: Controls access to the CUI, Data Register and Address
Latch. WE# is active low, and latches both address and data (command or
array) on its rising edge.
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