251308-008 Datasheet, PDF (33/91 Pages) Intel Corporation – Mobile Intel Celeron Processor on .13 Micron Process and in FCPGA Package

Electrical Specifications
Table 20. Miscellaneous Signals AC Specifications
T# Parameter
Min
T35: Asynch GTL+ Input Pulse Width
2
T36: PWRGOOD to RESET# de-assertion
time
1
T37: PWRGOOD Inactive Pulse Width
10
T38: PROCHOT# pulse width
500
T39: THERMTRIP# to Vcc Removal
T40: FERR# Valid Delay from STPCLK#
deassertion
0
Max
10
0.5
5
Unit
BCLKs
Figure
Notes^1,2,3,6
ms
15
BCLKs
us
s
15 4
17 5
18
BCLKs
19
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All AC timings for the Asynch GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage. All
Asynch GTL+ signal timings are referenced at GTLREF. PWRGOOD is referenced to the BCLK0 rising edge
at 0.5*V_CC
3. These signals may be driven asynchronously.
4. Refer to the PWRGOOD definition for more details regarding the behavior of this signal.
5. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the
assertion and before the deassertion of PROCHOT# for the processor to complete current instruction
execution. This specification refers to PROCHOT# when asserted by the processor. There are no pulse width
requirements for when PROCHOT# is asserted by the system.
6. See Section 7.2 for additional timing requirements for entering and leaving the low power states.
Table 21. FSB AC Specifications (Reset Conditions)
T# Parameter
Min
T45: Reset Configuration Signals (A[31:3]#,
BR0#, INIT#, SMI#) Setup Time
4
T46: Reset Configuration Signals (A[31:3]#,
BR0#, INIT#, SMI#) Hold Time
2
Max
Unit
BCLKs
20
BCLKs
Figure Notes
12
1
12
2
NOTES:
1. Before the deassertion of RESET#.
2. After clock that deasserts RESET#.
Datasheet
33