251308-008 Datasheet, PDF (11/91 Pages) Intel Corporation – Mobile Intel Celeron Processor on .13 Micron Process and in FCPGA Package

Electrical Specifications
2 Electrical Specifications
2.1
2.2
2.3
FSB and GTLREF
Most mobile Celeron processor FSB signals use Assisted Gunning Transceiver Logic (AGTL+)
signalling technology. As with the Intel P6 family of microprocessors, this signalling technology
provides improved noise margins and reduced ringing through low-voltage swings and controlled
edge rates. The termination voltage level for the mobile Celeron processor AGTL+ signals is V_CC,
which is the operating voltage of the processor core. Previous generations of Intel mobile
processors utilize a fixed termination voltage known as V_CCT. The use of a termination voltage that
is determined by the processor core allows better voltage scaling on the FSB for mobile Celeron
processor. Because of the speed improvements to data and address bus, signal integrity and
platform design methods have become more critical than with previous processor families. Design
guidelines for the mobile Celeron processor FSB will be detailed in the Mobile Intel^® Pentium^® 4
Processor-M and Intel^® 845MP/845MZ Chipset Platform Design Guide.
The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board.
Termination resistors are provided on the processor silicon and are terminated to its core voltage
(V_CC). Intel’s 845MP/845MZ chipsets will also provide on-die termination, thus eliminating the
need to terminate the bus on the system board for most AGTL+ signals. However, some AGTL+
signals do not include on-die termination and must be terminated on the system board. For more
information, refer to the Mobile Intel^® Pentium^® 4 Processor-M and Intel^® 845MP/845MZ
Chipset Platform Design Guide.
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
FSB, including trace lengths, is highly recommended when designing a system.
Power and Ground Pins
For clean on-chip power distribution, the mobile Celeron processor have 85 V_CC (power) and 181
V_SS (ground) inputs. All power pins must be connected to V_CC, while all V_SS pins must be
connected to a system ground plane.The processor V_CC pins must be supplied with the voltage
determined by the VID (Voltage ID) pins and the loadline specifications (see Figure 4 to Figure 5).
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. This may cause
voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.
Care must be taken in the board design to ensure that the voltage provided to the processor remains
within the specifications listed in Table 7. Failure to do so can result in timing violations and affect
Datasheet
11