410 Datasheet, PDF (22/71 Pages) Intel Corporation – Celeron M Processor on 65 nm Process

Electrical Specifications
Table 2.
3.5
3.6
Voltage Identification Definition (Sheet 4 of 4)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
V_CC(V)
1
1
1
0
0
0
1
0.0875
1
1
1
0
0
1
0
0.0750
1
1
1
0
0
1
1
0.0625
1
1
1
0
1
0
0
0.0500
1
1
1
0
1
0
1
0.0375
1
1
1
0
1
1
0
0.0250
1
1
1
0
1
1
1
0.0125
1
1
1
1
0
0
0
0.0000
NOTE: A “1” in this table refers to a high-voltage level and a “0” refers to low-voltage level. Contact your Intel
representative for further information on BIOS VID programming.
Catastrophic Thermal Protection
The Celeron M processor supports the THERMTRIP# signal for catastrophic thermal
protection. An external thermal sensor should also be used to protect the processor
and the system against excessive temperatures. Even with the activation of
THERMTRIP#, which halts all processor internal clocks and activity, leakage current can
be high enough such that the processor cannot be protected in all conditions without
the removal of power to the processor. If the external thermal sensor detects a
catastrophic processor temperature of 125°C (maximum), or if the THERMTRIP# signal
is asserted, the V_CC supply to the processor must be turned off within 500 ms to
prevent permanent silicon damage due to thermal runaway of the processor.
Signal Terminations and Unused Pins
All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to V_CC,
V_SS, or to any other signal (including each other) can result in component malfunction
or incompatibility with future Celeron M processors. See Section 4.4 for a pin listing of
the processor and the location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if
AGTL+ termination is provided on the processor silicon. Unused active high inputs
should be connected through a resistor to ground (V_SS). Unused outputs can be left
unconnected.
Please contact your Intel representative for details on signal terminations and TAP
signal termination requirements.
The TEST1 and TEST2 pins must have a stuffing option connection to V_SS separately via
1-kΩ, pull-down resistors. The TEST2 pin must have a 51-Ω ±5%, pull-down resistor to
V_SS.
22
Datasheet