410 Datasheet, PDF (15/71 Pages) Intel Corporation – Celeron M Processor on 65 nm Process

Low Power Features
2.1.2.5
2.2
Deep Sleep State
Deep Sleep state is a very low power state the processor can enter while maintaining
context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep
state. BCLK may be stopped during the Deep Sleep state for additional platform level
power savings. BCLK stop/restart timings on appropriate chipset based platforms with
the CK410M clock chip are as follows:
• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of
DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.
• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels
within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK
periods.
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-
started after DPSLP# deassertion as described above. A period of 15 microseconds (to
allow for PLL stabilization) must occur before the processor can be considered to be in
the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter
the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop
transactions or latching interrupt signals. No transitions of signals are allowed on the
FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep
state, it will not respond to interrupts or snoop transactions. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable
behavior.
FSB Low Power Enhancements
The Celeron M processor incorporates FSB low power enhancements:
• Dynamic FSB Power Down
• BPRI# control for address and control input buffers
• Dynamic Bus Parking
• Dynamic On Die Termination disabling
• Low V_CCP (I/O termination voltage)
The Celeron M processor incorporates the DPWR# signal that controls the data bus
input buffers on the processor. The DPWR# signal disables the buffers when not used
and activates them only when data bus activity occurs, resulting in significant power
savings with no performance impact. BPRI# control also allows the processor address
and control input buffers to be turned off when the BPRI# signal is inactive. Dynamic
Bus Parking allows a reciprocal power reduction in chipset address and control input
buffers when the processor deasserts its BR0# pin. The On Die Termination on the
processor FSB buffers is disabled when the signals are driven low, resulting in
additional power savings. The low I/O termination voltage is on a dedicated voltage
plane independent of the core voltage, enabling low I/O switching power at all times.
Datasheet
15