298020-002 Datasheet, PDF (21/166 Pages) Intel Corporation – Intel 840 Chipset 82840 Memory Controller Hub (MCH)

82840 MCH
R
2. Signal Description
This section provides a detailed description of MCH signals. The signals are arranged in functional
groups according to their associated interface.
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the
signal is at a low voltage level. When “#” is not present after the signal name the signal is asserted when
at the high voltage level.
The following notations are used to describe the signal type:
I
Input pin
O
Output pin
I/O
Bi-directional Input/Output pin
s/t/s
Sustained Tristate. This pin is driven to its inactive state prior to tri-stating.
as/t/s
Active Sustained Tristate. This applies to some of the hub interface signals. This pin is weakly
driven to its last driven value.
The signal description also includes the type of buffer used for the particular signal:
GTL+ Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for complete details.
AGP
AGP interface signals. These signals can be programmed to be compatible with AGP 2.0 3.3v
or 1.5v Signaling Environment DC and AC Specifications. In 3.3v mode the buffers are not 5v
tolerant. In 1.5v mode the buffers are not 3.3v tolerant.
CMOS CMOS buffers.
RSL Rambus* Signaling Level interface signal.
Datasheet
21