298020-002 Datasheet, PDF (139/166 Pages) Intel Corporation – Intel 840 Chipset 82840 Memory Controller Hub (MCH)

82840 MCH
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5.3.2.1. Row Packet (ROWA/ROWR)
The row packet is defined using three RSL signals RQ[7:5]/ROW[2:0]. The row packet is generally the
first control packet issued to a device. Major characteristics of a row packet are:
• The only way to activate (sense) a row within a bank
• Independent of Direct RDRAM’s active/standby state
• A non-broadcast row package causes an addressed Direct RDRAM to move to active state
The packet definition of row packet is provided in the following table.
Table 19. ROWA Packet for Activating (sensing) a Row (i.e., AV = 1)
Row #
Cycle 0
Cycle 1
Cycle 2
ROW2
DR4T
DR[2]
BR[0]
BR[3]
R[10]
R[8]
ROW1
DR4F
D[R1]
BR[1]
BR[4]
R[9]
R[7]
ROW0
DR[3]
DR[0]
BR[2]
REV
AV = 1
R[6]
Cycle 3
R[5]
R[2]
R[4]
R[1]
R[3]
R[0]
Table 20. ROWR Packet for other operations (i.e., AV = 0)
Row #
Cycle 0
Cycle 1
ROW2
ROW1
ROW0
DR4T
DR4F
DR[3]
DR[2]
DR[1]
DR[0]
BR[0]
BR[1]
BR[2]
BR[3]
BR[4]
REV
Cycle 2
ROP[10]
ROP[9]
AV = 0
ROP[8]
ROP[7]
ROP[6]
Cycle 3
ROP[5]
ROP[4]
ROP[3]
ROP[2]
ROP[1]
ROP[0]
DR4T
0
0
1
1
DR4F
0
1
0
1
Device ID
No row packet
DR[3:0], DR[4] = 0
DR[3:0], DR[4] = 1
Broadcast
DR[4] – DR[0]
BR[5] – BR[0]
R[10] – R[0]
AV
ROP[10] – ROP[0]
REV
Device address
Bank Address
Row address
Select between ROWA and ROWR, Active Row
Opcode for Primary Control Packet
Reserved
Datasheet
139