82599_10 Datasheet, PDF (2/4 Pages) Intel Corporation – Transforming the data center through a reliable and unified 10GbE network

Virtual Machine Direct Connect (VMDc). VMDq improves data
processing by offloading the sorting and queuing functionality
to the I/O controller from the VMM. VMDc provides direct con-
nectivity to the VMs to deliver near-native performance and VM
scalability. VMDc also provides flexibility with mobility by enabling
VM migration between physical servers. VMDc is based on the
industry-standard PCI-SIG SR-IOV (Single Root I/O Virtualization).
Unified Networking
Intel 82599 10 Gigabit Ethernet controller reduces cost and
complexity of the data center by combining LAN and SAN traffic
onto a single Ethernet fabric. Customers can use iSCSI, NAS or
FCoE to carry storage traffic over Ethernet. In order to meet
SAN requirements for guaranteed packet delivery, the controller
implements capabilities such as enhanced transmission selecting
and priority flow control. The controller accelerates iSCSI traffic by
implementing key stateless offloads such as TCP segmentation
offload (TSO) and Receive Side Coalescing (RSC). It also supports
the trusted iSCSI initiators from Microsoft, Linux,* and VMware
operating systems and provides a robust iSCSI remote boot
implementation. Further, the Intel 82599 10 Gigabit Ethernet
controller delivers a high performing FCoE solution that offloads
the main data paths for I/O read and write commands. It also
greatly reduces CPU processing on FCoE receive traffic by eliminat-
ing a data copy through Direct Data placement implementation.
Integrated Solution for LAN
on Motherboard (LOM)
The Intel 82599 10 Gigabit Ethernet controller it is a single-chip,
dual-port 10GbE implementation in a 25x25 mm package. It
reduces BOM cost and design complexity by integrating serial
10GbE PHYs and provides both SFI and KR interfaces. The device
is designed for high performance and lower memory latency.
Wide internal data paths eliminate performance bottlenecks by
efficiently handling large address and data words. The controller
also includes advanced interrupt-handling features and uses
efficient ring-buffer descriptor data structures, with up to 64
packet descriptors. A large on-chip packet buffer maintains superior
performance. The controller enables network manageability
implementations required by IT personnel for remote control
and alerting. The communication to the Board Management
Controller (BMC) is available either through an on-board System
Management BUS (SMBus) port or though the DMTF-defined NC-SI.
With industry-leading power consumption, a small footprint, and
integrated PHYs, the controller is ideally suited for Server Blades,
LAN on motherboard (LOM), NIC, and Mezzanine card implemen-
tations. The advanced features of the Intel 82599 10 Gigabit
Ethernet controller along with the Intel Xeon processor 5500
series enable customers to scale volume servers to fully utilize
and scale to 10GbE capacity.
Features
Host Interface Features
PCI Express* 2.0 (5 GT/s)
Compatible extensions to PCI power management and ACPI
End to End CRC (ECRC)
Benefits
• Supports x8, x4, x2, x1 lanes
• Supports extended error reporting and completion timeout control
• Efficient power management
• Higher reliability on PCI bus traffic
Network Interface Features
XAUI, KX/KX4, BX, CX4
10GBASE-KR
SFP+ MSA (SFI)
NC-SI Interface
100 Mbps/1 Gbps/10 Gbps speeds
• Multiple interfaces for design flexibility
• Serial 10GbE backplane interface for simpler blade implementation
• Support for Auto-negotiation and PCS layer
• Native support for SFI interface
• Saves BOM cost and reduces design complexity by integrating XAUI to SFI PHYs
• Management interfaces for pass-through traffic to and from manageability controller
• Triple-speed support for backward-compatible implementations
10 Gigabit MAC Advanced Features
Dual configurable first-in/first-out (FIFO) buffers for each port:
160 KB Transmit (Tx) and 512 KB Receive (Rx)
Support for transmission and reception of packets up to
15.5 KBytes (Jumbo Frames) in basic mode and 9.5 Kbytes
packets when DCB or Virtualization is enabled.
Programmable host memory receive buffer per queue
(1 KByte to 16 KBytes) and cache line size (64 Bytes
to 128 Bytes)
Descriptor ring management hardware for Tx/Rx optimized
descriptor fetching and write-back mechanisms
• No external FIFO memory requirements
• FIFO size adjustable to application
• Error detection and correction for FIFO data
• Enables higher and better throughput of data
• Efficient use of PCI Express bandwidth
• Simple software programming model
• Efficient use of system memory and PCI Express bandwidth
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