28F008C3 Datasheet, PDF (18/59 Pages) Intel Corporation – 3 VOLT ADVANCED+ BOOT BLOCK 8-, 16-, 32-MBIT FLASH MEMORY FAMILY

3 VOLT ADVANCED+ BOOT BLOCK
E
Table 7. Status Register Bit Definition
WSMS
ESS
ES
PS
VPPS
PSS
BLS
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 WRITE STATE MACHINE STATUS
1 = Ready
(WSMS)
0 = Busy
Check Write State Machine bit first to determine Word
Program or Block Erase completion, before checking
Program or Erase Status bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts execution
and sets both WSMS and ESS bits to “1.” ESS bit
remains set to “1” until an Erase Resume command is
issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erase
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the max.
number of erase pulses to the block and is still unable to
verify successful block erasure.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
When this bit is set to “1,” WSM has attempted but failed
to program a word/byte.
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.2 = PROGRAM SUSPEND STATUS
(PSS)
1 = Program Suspended
0 = Program in Progress/Completed
The VPP status bit does not provide continuous indication
of VPP level. The WSM interrogates VPP level only after
the Program or Erase command sequences have been
entered, and informs the system if VPP has not been
switched on. The VPP is also checked before the
operation is verified by the WSM. The VPP status bit is
not guaranteed to report accurate feedback between
VPPLK and VPP1Min.
When Program Suspend is issued, WSM halts execution
and sets both WSMS and PSS bits to “1.” PSS bit
remains set to “1” until a Program Resume command is
issued.
SR.1 = BLOCK LOCK STATUS
1 = Prog/Erase attempted on a locked
block; Operation aborted.
0 = No operation to locked blocks
If a program or erase operation is attempted to one of the
locked blocks, this bit is set by the WSM. The operation
specified is aborted and the device is returned to read
status mode.
SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
This bit is reserved for future use and should be masked
out when polling the status register.
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