E7500 Datasheet, PDF (13/15 Pages) Intel Corporation – Intel® E7500 Chipset Memory Controller Hub (MCH)

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Intel^® E7500 Memory Controller Hub (MCH)
Specification Clarifications
1.
Section 3.6.16 DRAM Row Boundary Register
Locked cycles to out of bounds memory locations (i.e. – locations above the top of total memory) are not
supported. Typically both locked and unlocked cycles to out fo bounds memory locations will result in
all 1s being returned on the system bus. Infrequently, however, locked cycles to these regions can result
in unpredicable Intel® E7500 Chipset MCH behavior.
2.
Secion 4.1 System Memory Spaces
Locked cycles to out of bounds memory locations (i.e. – locations above the top of total memory) are not
supported. Typically both locked and unlocked cycles to out fo bounds memory locations will result in
all 1s being returned on the system bus. Infrequently, however, locked cycles to these regions can result
in unpredicable Intel® E7500 Chipset MCH behavior.
Specification Update
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