E7500 Datasheet, PDF (11/15 Pages) Intel Corporation – Intel® E7500 Chipset Memory Controller Hub (MCH)

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Errata
Intel^® E7500 Memory Controller Hub (MCH)
1.
System Bus Strobe Glitch Falsely Reported
Problem:
The Intel^® E7500 Chipset MCH logic that monitors the system bus for data strobe glitches incorrectly
detects a glitch even though no glitch has occurred.
Implication: SYSBUS_FERR bit [1], SYSBUS_NERR bit [1], and FERR_GLOBAL bit [16] will falsely report that a
system bus error has been detected. Clearing these bits is not possible, as they are incorrectly set on
every system bus transaction.
Workaround: Monitor SYSBUS_NERR for system bus errors, ignoring bit [1].
Status:
Fixed in the MCH A3 stepping.
2.
Data Corruption In Mixed x4 / x8 DIMM Configurations
Problem:
Read data on the DDR memory interface is latched into an input FIFO using either all of the DQS signals
(when reading from a DIMM with x4 devices) or only the lower half of the DQS signals (when reading
from a DIMM with x8 devices). When a system is populated with both x4 and x8 DIMMs, an internal
MUX is used to switch between using all or half of the DQS signals to latch the FIFO (depending on
which DIMM is being accessed). When the internal MUX select signal switches, the MUX outputs may
incorrectly signal the FIFO to latch data.
Implication: Data corruption has been observed on the DDR memory interface when system configurations include
mixing of x4 and x8 DIMM types.
Workaround: Populate homogenous DIMM configurations only (all x4 DIMMs or all x8 DIMMs)
Status:
Fixed in the MCH A3 stepping.
Specification Update
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