82575EB Datasheet, PDF (13/62 Pages) Intel Corporation – Intel® 82575EB Gigabit Ethernet Controller Datasheet

System Management Interface Signals — Intel^® 82575EB Gigabit Ethernet Controller
3.4 System Management Interface Signals
Symbol
SMBCLK
SMBD
SMBALRT_N
NCSI_CLK_IN
NCSI_CLK_OUT
NCSI_CRS_DV
NCSI_RXD[1]
NCSI_RXD[0]
NCSI_TX_EN
NCSI_TXD[1]
NCSI_TXD[0]
Type
OD
OD
OD
I
O
O
O
Name and Function
SMB Clock
The SMB Clock signal is an open drain signals for the serial SMB interface.
SMB Data
The SMB Data signal is an open drain signal for the serial SMB interface.
SMB Alert
The SMB Alert signal is an open drain signal for serial SMB Port A.It acts as an alert input in
82559 compatible mode.
NCSI Reference Clock Input. Synchronous clock reference for receive, transmit and control
interface. It is a 50MHz clock /- 50 ppm.
NCSI Reference Clock Output. Synchronous clock reference for receive, transmit and
control interface. It is a 50MHz clock /- 50 ppm. Serves as a clock source to the BMC and
the 82575EB (when configured so).
Carrier Sense / Receive Data Valid
Receive Data. Data signals from the device to the BMC
I
Transmit Enable
I
Transmit Data. Data signals from BMC to the device
3.5 MDIO Signals
Symbol
MDC
MDIO
Type
O
I/O
Name and Function
Management Data Clock. Used by the PHY as a clock timing reference for information transfer on
the MDIO signal. The MDC is not required to be a continuous signal and can be frozen when no
management data is transferred. The MDC signal has a maximum operating frequency of
2.5MHz.
Management Data I/O. This internal signaling between the MAC and PHY logically represents a
bi-directional data signal used to transfer control information and status to and from the PHY (to
read and write the PHY management registers ). Asserting and interpreting value(s) on this
interface requires knowledge of the special MDIO protocol to avoid possible internal signal
contention or miscommunication to/from the PHY
3.6 SPI EEPROM and FLASH Signals
Symbol
EE_DI
EE_DO
EE_CS_N
Type
TS
I
TS
Name and Function
EEPROM Data Input
The EEPROM Data Input pin is used for output to the SPI EEPROM memory device.
EEPROM Data Output
The EEPROM Data Output pin is used for input from the SPI EEPROM memory device. The EE_DO
includes an internal pull-up resistor.
EEPROM Chip Select
The EEPROM Chip Select signal is used to enable the device.
317679-004
Revision: 2.11
January 2011
Intel^® 82575EB Gigabit Ethernet Controller
Datasheet
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