28F016XD Datasheet, PDF (13/54 Pages) Intel Corporation – 16-MBIT (1 MBIT x 16) DRAM-INTERFACE FLASH MEMORY

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28F016XD FLASH MEMORY
4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
4.1 Bus Operations
Mode
Row Address Latch
Column Address Latch
Read
Output Disable
Standby
Deep Power-Down
Manufacturer ID
Device ID
Write
Notes
1,2,9
1,2,9
1,2,7
1,6,7
1,6,7
1,3
4,8
4,8
1,5,6
RP#
V_IH
V_IH
V_IH
V_IH
V_IH
V_IL
V_IH
V_IH
V_IH
RAS# CAS#
↓
V_IH
V_IL
↓
V_IL
V_IL
V_IL
V_IL
V_IH
V_IH
X
X
V_IL
V_IL
V_IL
V_IL
V_IL
V_IL
OE#
X
X
V_IL
V_IH
X
X
V_IL
V_IL
X
WE#
X
X
V_IH
V_IH
X
X
V_IH
V_IH
V_IL
DQ_0–15
X
X
D_OUT
High Z
High Z
High Z
0089H
66A8H
D_IN
RY/BY#
X
X
X
X
X
V_OH
V_OH
V_OH
X
NOTES:
1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH, or High Z or DOUT for data
pins depending on whether or not OE# is active.
2. RY/BY# output is open drain. When the WSM is ready, erase is suspended or the device is in deep power-down mode,
RY/BY# will be at VOH if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM operation
is in progress.
3. RP# at GND ± 0.2V ensures the lowest deep power-down current.
4. A0 (latched by CAS#) at VIL provides the Manufacturer ID code. A0 (latched by CAS#) at VIH provides the Device ID code.
All other addresses (row and column) should be set to zero.
5. Commands for erase, data program, or lock-block operations can only be completed successfully when VPP = VPPH1 or
VPP = VPPH2.
6. While the WSM is running, RY/BY# stays at VOL until all operations are complete. RY/BY# goes to VOH when the WSM is
not busy or in erase suspend mode.
7. RY/BY# may be at VOL while the WSM is busy performing various operations (for example, a Status Register read during a
program operation).
8. The 28F016XD shares an identical device identifier with the 28F016XS.
9. Row (upper) addresses are latched via inputs A0-9 on the falling edge of RAS#. Column (lower) addresses are latched via
inputs A0-9 on the falling edge of CAS#. Row addresses must be latched before column addresses are latched.
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