313953-002 Datasheet, PDF (129/218 Pages) Intel Corporation – Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH)

Host-PCI Express Bridge Registers (D3:F0) (Intel® 3010 Chipset only)
6 Host-PCI Express Bridge
Registers (D3:F0) (Intel®
3010 Chipset only)
This chapter is for the Intel® 3010 chipset only.
Device 3 contains the controls associated with the PCI Express root port. In addition, it
also functions as the virtual PCI-to-PCI bridge. Table 6-1 provides an address map of
the D3:F0 registers listed by address offset in ascending order. Section 6.1 provides a
detailed bit description of the registers.
Warning:
When reading the PCI Express “conceptual” registers such as this, you may not get a
valid value unless the register value is stable.
The PCI Express Specification defines two types of reserved bits: Reserved and
Preserved:
1. Reserved for future RW implementations; software must preserve value read for
writes to bits.
2. Reserved and Zero: Reserved for future R/WC/S implementations; software must
use 0 for writes to bits.
Unless explicitly documented as Reserved and Zero, all bits marked as reserved are
part of the Reserved and Preserved type, which have historically been the typical
definition for Reserved.
It is important to note that most (if not all) control bits in this device cannot be
modified unless the link is down. Software is required to first Disable the link, then
program the registers, and then re-enable the link (which will cause a full-retrain with
the new settings).
Table 6-1.
Host-PCI Express Bridge Register Address Map (D3:F0) (Sheet 1 of 3)
Address
Offset
00-01h
02-03h
04-05h
06-07h
08h
09-0Bh
0Ch
0Dh
0Eh
0F-17h
18h
19h
1Ah
Register Symbol
Register Name
VID3
DID3
PCICMD3
PCISTS3
RID3
CC3
CL3
—
HDR3
—
PBUSN3
SBUSN3
SUBUSN3
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Class Code
Cache Line Size
Reserved
Header Type
Reserved
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Default Value
8086h
277Ah
0000h
0010h
C0h
060400h
00h
—
01h
—
00h
00h
00h
Access
RO
RO
RO, R/W
RO, R/WC
RO
RO
R/W
—
RO
—
RO
RO
R/W
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
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