313953-002 Datasheet, PDF (114/218 Pages) Intel Corporation – Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH)

Host-PCI Express Bridge Registers (D1:F0)
5.1.43
5.1.44
SLOTSTS—Slot Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
BAh
0000h
RO, R/W/C
16 bits
PCI Express slot-related registers allow for the support of Hot-Plug.
Bit
15:7
6
5
4
3
2:1
0
Access &
Default
RO
0b
R/WC
0b
R/WC
0b
R/WC
0b
Description
Reserved
Presence Detect State
Indicates the presence of a card in the slot.
0: Slot Empty
1: Card Present in slot.
Reserved
Command Completed
Set when the hot plug controller completes an issued command.
Presence Detect Changed
Set when a Presence Detect change is detected. This corresponds to an edge on
the signal that corresponds to bit 6 of this register (Presence Detect State).
Reserved
Attention Button Pressed
Set when the Attention Button is pressed.
RCTL—Root Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
BCh
0000h
R/W
16 bits
Allows control of PCI Express Root Complex specific parameters. The system error
control bits in this register determine if corresponding SERRs are generated when our
device detects an error (reported in this device’s Device Status register) or when an
error message is received across the link. Reporting of SERR as controlled by these bits
takes precedence over the SERR Enable in the PCI Command Register.
Bit
15:4
3
Access &
Default
R/W
0b
Description
Reserved
PME Interrupt Enable
0: No interrupts are generated as a result of receiving PME messages.
1: Enables interrupt generation upon receipt of a PME message as reflected in the
PME Status bit of the Root Status Register. A PME interrupt is also generated if
the PME Status bit of the Root Status Register is set when this bit is set from a
cleared state.
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Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet