A28F010 Datasheet, PDF(12/23 Page) Intel Corporation – 1024K (128K x 8) CMOS FLASH MEMORY

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A28F010 Datasheet, PDF (12/23 Pages) Intel Corporation – 1024K (128K x 8) CMOS FLASH MEMORY

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A28F010

DESIGN CONSIDERATIONS

Two-Line Output Control

Flash-memories are often used in larger memory ar-

rays Intel provides two read-control inputs to ac-

commodate multiple memory connections Two-line

control provides for

a the lowest possible memory power dissipation

and

b complete assurance that output bus contention

will not occur

To efficiently use these two control inputs an ad-

dress-decoder output should drive chip-enable

while the systemâs read signal controls all flash-

memories and other parallel memories This assures

that only enabled memory devices have active out-

puts while deselected devices maintain the low

power standby condition

Power Supply Decoupling

Flash memory power-switching characteristics re-

quire careful device decoupling System designers

are interested in three supply current (ICC) issues

standby active and transient current peaks pro-

duced by falling and rising edges of chip-enable The

capacitive and inductive loads on the device outputs

determine the magnitudes of these peaks

Two-line control and proper decoupling capacitor

selection will suppress transient voltage peaks

Each device should have a 0 1 mF ceramic capacitor

connected between VCC and VSS and between VPP

and VSS

Place the high-frequency low-inherent-inductance

capacitors as close as possible to the devices Also

for every eight devices a 4 7 mF electrolytic capaci-

tor should be placed at the arrayâs power supply

connection between VCC and VSS The bulk capaci-

tor will overcome voltage slumps caused by printed-

circuit-board trace inductance and will supply

charge to the smaller capacitors as needed

VPP Trace on Printed Circuit Boards

Programming flash-memories while they reside in

the target system requires that the printed circuit

board designer pay attention to the VPP power sup-

ply trace The VPP pin supplies the memory cell cur-

rent for programming Use similar trace widths and

layout considerations given the VCC power bus Ad-

equate VPP supply traces and decoupling will de-

crease VPP voltage spikes and overshoots

Power Up Down Protection

The 28F010 is designed to offer protection against

accidental erasure or programming caused by spur-

ious system-level signals that may exist during pow-

er transitions Also with its control register architec-

ture alteration of memory contents only occurs after

successful completion of the two-step command se-

quences Power supply sequencing is not required

Internal circuitry of the 28F010 ensures that the

command register architecture is reset to the read

mode on power up

A system designer must guard against active writes

for VCC voltages above the VLKO when VPP is ac-

tive Since both WE and CE must be low for a

command write driving either to VIH will prohibit

writes The control register architecture provides an

added level of protection since alteration of memory

contents only occurs after successful completion of

the two-step command sequences

28F010 Power Dissipation

When designing portable systems designers must

consider battery power consumption not only during

device operation but also for data retention during

system idle time Flash nonvolatility increases the

usable battery life of your system because the

28F010 does not consume any power to retain code

or data when the system is off Table 4 illustrates the

power dissipated when updating the 28F010

Table 4 28F010 Typical Update

Power Dissipation(4)

Operation

Power Dissipation

(Watt-Seconds)

Notes

Array Program

0 171

Program Verify

Array Erase

Erase Verify

0 136

One Complete

0 478

Cycle

NOTES

1 Formula to calculate typical Program Program Verify

Power e VPP c Bytes c typical Prog Pulses

(tWHWH1 c IPP2 typical a tWHGL c IPP4 typical) a VCC

c Bytes c typical Prog Pulses (tWHWH1 c ICC2 typi-

cal a tWHGL c ICC4 typical

2 Formula to calculate typical Erase Erase Verify Power

e VPP (VPP3 typical c tERASE typical a IPP5 typical c

tWHGL c Bytes) a VCC (ICC3 typical c tERASE typical

c ICC5 typical c tWHGL c Bytes)

3 One Complete Cycle e Array Preprogram a Array

Erase a Program

4 ââTypicalsââ are not guaranteed but based on a limited

number of samples from production lots

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