IXP2400 Datasheet, PDF (10/126 Pages) Intel Corporation – Intel® IXP2400 Network Processor

Intel^® IXP2400 Network Processor
2.0
Functional Units
2.1
Functional Overview
This section provides a brief overview of the IXP2400 Network Processor internal hardware.
Figure 4 is a simple block diagram that shows the device’s major internal blocks.
Figure 4. IXP2400 Network Processor Chassis Concept Block Diagram
Media Switch
Fabric (MSF)
Scratchpad
Memory
SRAM
Controller
0
SRAM
Controller
1
DRAM
Controller
Hash
Unit
PCI
Controller
CAP
ME
0x1
ME
0x0
ME
ME
0x2
0x3
ME Cluster 0
ME
0x10
ME
0x11
ME
0x13
ME
0x12
ME Cluster 1
Intel
XScale®
Core
Peripherals
(XPI)
Intel
XScale®
Core
Performance
Monitor
A9811-01
The major blocks are:
• Intel XScale core — General-purpose 32-bit RISC processor compatible to ARM Version 5
Architecture. The Intel XScale core is used to initialize and manage the chip, and can be used
for higher layer network processing tasks.
• Microengines (MEs) — 8 32-bit programmable engines specialized for network processing.
Microengines do the main data plane processing per packet.
• DRAM Controller — 1 DDR SDRAM controller. Typically DRAM is used for data buffer
storage.
• SRAM Controller — 2 independent controllers for QDR SRAM. Typically SRAM is used for
control information storage.
• Scratchpad Memory — 16 Kbytes of storage for general-purpose use.
• Media and Switch Fabric Interface (MSF) — Interface for network framers and/or Switch
Fabric. Contains receive and transmit buffers.
• Hash Unit — Polynomial hash accelerator. The Intel XScale core and Microengines can use it
to offload hash calculations.
• PCI Controller — 64-bit PCI Rev 2.2 compliant IO bus. PCI can be used to either connect to a
Host processor, or to attach PCI-compliant peripheral devices.
10
Datasheet