IXP2400 Datasheet, PDF (1/126 Pages) Intel Corporation – Intel® IXP2400 Network Processor

Intel^® IXP2400 Network Processor
Datasheet
Product Features
The Intel^® IXP2400 Network Processor enables faster deployment of intelligent
network services by providing high programming flexibility, code re-use, and
high-performance processing. IXP2400 Network Processor supports a wide
variety of WAN and LAN applications requiring support for a broad range of
speeds, currently ranging from OC-3 to OC-48. High performance and
scalability is achieved through an innovative Microengine architecture that
includes a multi-threaded distribution cache architecture that enables pipeline
features in software. The Microengines feature innovative inter-thread
communication capabilities for efficient processing at high line rates, and
general-purpose hardware elements that support advanced networking
algorithms. The Microengines play a key role in the Intel^® Exchange
Architecture (IXA) store and forward architecture, providing flexible, rich
network processing in converged communications environments.
■ Eight integrated Microengine Version 2 ■ Industry-standard PCI Bus Version 2.2
Processors
interface for 64-bit, 66-MHz I/O
— Operating frequencies of 400 and 600 MHz _{■ Industry-standard double-data-rate (DDR)}
— Configurable to four or eight threads per
SDRAM memory interface
Microengine
— Peak bandwidth of 2.4 GB/s
— 640 x 32-bit local memory per Microengine
— Clock speeds of 100, 150 MHz supported
— Sixteen-entry CAM per Microengine with
when IXP2400 is running at 600 MHz; 100
single cycle lookup
MHz when IXP2400 is running at 400 MHz
— Next Neighbor bus: A dedicated datapath
— Error correction code (ECC)
between adjacent Microengines
— Addressable from the Intel XScale core, MEs,
— CRC unit per Microengine supporting
and PCI
CRC-16 (CCITT) and CRC-32
— 4K-instruction control store per Microengine ^{■ Two industry-standard 32-bit quad-data-rate}
— Support for Generalized Thread Signaling
(QDR) SRAM interfaces
— Reflector access to read or write data between ^{— Peak bandwidth of 1.6 GB/s per channel}
any Microengines
— 100- or 133-MHz SRAM when IXP2400 is
running at 400 MHz; 100-, 150- or 200-MHz
■ Integrated Intel XScale core
SRAM when IXP2400 is running at 600 MHz
— Operating frequencies of 400 and 600 MHz
— Hardware support for Linked List and Ring
— High-performance, low-power, 32-bit
operations
embedded RISC processor
— Atomic bit operations
— 32-Kbyte instruction cache
— Atomic arithmetic support
— 32-Kbyte data cache
— Addressable from the Intel XScale core, MEs,
— 2-Kbyte mini data cache
and PCI
■ Two uni-directional 32-bit low-voltage
transistor-transistor logic (LVTTL) data
interfaces
— Speeds from 25 to 133 MHz supported
— Separately configurable for POS-PHY,
UTOPIA 1/2/3, or CSIX-L1-B Protocol
support
— Interprocessor “Cbus” communication
■ Additional integrated features
— Hardware hash unit (48, 64 and 128 bit)
— 16-Kbyte scratchpad memory
— Serial port for debug
— Eight general-purpose I/O pins
— Four 32-bit timers
■ 1356-Ball FCBGA2 package
— Dimensions of 37.5 mm x 37.5 mm
— 1 mm solder ball pitch
Notice: Please verify with your local Intel sales office that you have the latest datasheet before
finalizing a design.
February 2004
Document Number: 301164-011