AN87C196KDF8 Datasheet, PDF (10/21 Pages) Intel Corporation – 16-BIT HIGH PERFORMANCE CHMOS MICROCONTROLLER

AUTOMOTIVE 87C196KD
AC CHARACTERISTICS (Continued)
For use over specified operating conditions
Test Conditions Capacitive load on all pins ^e 100 pF Rise and fall times ^e 10 ns F_OSC ^e 16 MHz
The 87C196KD will meet these specifications
Symbol
Description
F_XTAL
T_OSC
T_XHCH
T_CLCL
T_CHCL
T_CLLH
T_LLCH
T_LHLH
T_LHLL
T_AVLL
T_LLAX
T_LLRL
T_RLCL
T_RLRH
T_RHLH
T_RLAZ
T_LLWL
T_CLWL
T_QVWH
T_CHWH
T_WLWH
T_WHQX
T_WHLH
T_WHBX
T_WHAX
T_RHBX
T_RHAX
Frequency on XTAL₁
I F_XTAL
XTAL1 High to CLKOUT High or Low
CLKOUT Cycle Time
CLKOUT High Period
CLKOUT Falling Edge to ALE Rising
ALE Falling Edge to CLKOUT Rising
ALE Cycle Time
ALE High Period
Address Setup to ALE Falling Edge
Address Hold after ALE Falling Edge
ALE Falling Edge to RD Falling Edge
RD Low to CLKOUT Falling Edge
RD Low Period
RD Rising Edge to ALE Rising Edge
RD Low to Address Float
ALE Falling Edge to WR Falling Edge
CLKOUT Low to WR Falling Edge
Data Stable to WR Rising Edge
CLKOUT High to WR Rising Edge
WR Low Period
Data Hold after WR Rising Edge
WR Rising Edge to ALE Rising Edge
BHE INST after WR Rising Edge
AD8–15 HOLD after WR Rising
BHE INST after RD Rising Edge
AD8–15 HOLD after RD Rising
Min
Max
40
16
62 5
250
20
110
2 T_OSC
T_OSC ^b 10
T_OSC^a15
b₅
15
b₂₅
a₁₅
4 T_OSC
T_OSC ^b 10
T_OSC^a10
T_OSC ^b 15
T_OSC ^b 35
T_OSC ^b 35
0
35
T_OSC ^b 5
T_OSC
T_OSC ^a 25
5
T_OSC ^b 10
0
25
T_OSC ^b 30
b₅
15
T_OSC ^b 30
T_OSC ^b 25
T_OSC ^b 10
T_OSC ^b 10
T_OSC ^b 30
T_OSC ^b 10
T_OSC ^b 25
T_OSC ^a 15
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
(Note 1)
(Note 4)
(Note 4)
(Note 2)
(Note 4)
(Note 4)
(Note 2)
(Note 3)
(Note 3)
NOTES
1 Testing performed at 4 0 MHz However the device is static by design and will typically operate below 1 Hz
2 Assuming back-to-back bus cycles
3 8-Bit bus only
4 If wait states are used add 2 T_OSC N where N e number of wait states
10