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28F640L18 Datasheet, PDF (1/106 Pages) Intel Corporation – StrataFlash Wireless Memory | |||
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Intel StrataFlash® Wireless Memory
(L18)
28F640L18, 28F128L18, 28F256L18
Datasheet
Product Features
â High performance Read-While-Write/Erase
â 85 ns initial access
â 54 MHz with zero wait state, 14 ns clock-to-
data output synchronous-burst mode
â 25 ns asynchronous-page mode
â 4-, 8-, 16-, and continuous-word burst mode
â Burst suspend
â Programmable WAIT configuration
â Buffered Enhanced Factory Programming
(BEFP) at 5 µs/byte (Typ)
â 1.8 V low-power buffered programming at
7 µs/byte (Typ)
â Architecture
â Asymmetrically-blocked architecture
â Multiple 8-Mbit partitions: 64-Mbit and 128-
Mbit devices
â Multiple 16-Mbit partitions: 256-Mbit devices
â Four 16-Kword parameter blocks: top or
bottom configurations
â 64-Kword main blocks
â Dual-operation: Read-While-Write (RWW) or
Read-While-Erase (RWE)
â Status Register for partition and device status
â Power
â VCC (core) = 1.7 V - 2.0 V
â VCCQ (I/O) = 1.35 V - 2.0 V, 1.7 V - 2.0 V
â Standby current: 30 µA (Typ) for 256-Mbit
â 4-Word synchronous read current: 15 mA (Typ)
at 54 MHz
â Automatic Power Savings mode
â Security
â OTP space:
⢠64 unique factory device identifier bits
⢠64 user-programmable OTP bits
⢠Additional 2048 user-programmable OTP bits
â Absolute write protection: VPP = GND
â Power-transition erase/program lockout
â Individual zero-latency block locking
â Individual block lock-down
â Software
â 20 µs (Typ) program suspend
â 20 µs (Typ) erase suspend
â Intel® Flash Data Integrator optimized
â Basic Command Set (BCS) and Extended
Command Set (ECS) compatible
â Common Flash Interface (CFI) capable
â Quality and Reliability
â Expanded temperature: â25° C to +85° C
â Minimum 100,000 erase cycles per block
â ETOX⢠VIII process technology (0.13 µm)
â Density and Packaging
â 64-, 128-, and 256-Mbit density in VF BGA
packages
â 128/0 and 256/0 density in SCSP
â 16-bit wide data bus
The Intel StrataFlash® wireless memory (L18) device is the latest generation of Intel
StrataFlash® memory devices featuring flexible, multiple-partition, dual operation. It provides
high performance synchronous-burst read mode and asynchronous read mode using 1.8 V low-
voltage, multi-level cell (MLC) technology.
The multiple-partition architecture enables background programming or erasing to occur in one
partition while code execution or data reads take place in another partition. This dual-operation
architecture also allows a system to interleave code operations while program and erase
operations take place in the background. The 8-Mbit or 16-Mbit partitions allow system
designers to choose the size of the code and data segments. The L18 wireless memory device is
manufactured using Intel 0.13 µm ETOX⢠VIII process technology. It is available in industry-
standard chip scale packaging.
Order Number: 251902, Revision: 009
April 2005
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