IN82C55AN Datasheet, PDF (20/21 Pages) Integral Corp. – CHMOS PROGRAMMABLE PERIPHERAL INTERFACE

IN82C55AN
OTHER TIMINGS
Symbol
Parameter
t_WB
WR = 1 to Output
t_lR
Peripheral Data Before RD
t_HR Peripheral Data After RD
t_AK
ACK Pulse Width
t_ST
STB Pulse Width
t_PS Per. Data Before STB High
t_PH Per. Data After STB High
t_AD
ACK = 0 to Output
t_KD
ACK = 1 to Output Float
t_WOB WR = 1 to OBF = 0
t_AOB
ACK = 0 to OBF = 1
t_SIB
STB = 0 to IBF = 1
t_RIB
RD = 1 to IBF = 0
t_RIT
RD = 0 to INTR = 0
t_SIT
STB = 1 to INTR = 1
t_AIT
ACK = 1 to INTR = 1
t_WIT
WR = 0 to INTR = 0
t_RES Reset Pulse Width
Min Max Units
350 ns
0
ns
0
ns
200
ns
100
ns
20
ns
Test
Conditions
50
ns
175 ns
20 250 ns
150 ns
150 ns
150 ns
150 ns
200 ns
150 ns
150 ns
200 ns see note1
500
ns see note2
NOTE
1. INTR_ may occur as early as WR _.
2. Pulse width of initial Reset pulse after power on must be at least 50µSec. Subsequent Reset pulses may
be 500ns minimum. The output Ports A B or C may glitch low during the reset pulse but all port pins will
be held at a logic “one” level after the reset pulse.
WRITE TIMING
A_0-1,CS
t_AW
t_WA
DATA BUS
t_DW
t_WD
WR
t_WW
20