IN74HC573 Datasheet, PDF (1/5 Pages) Integral Corp. – Octal 3-State Noninverting Transparent Latch

TECHNICAL DATA
Octal 3-State Noninverting
Transparent Latch
High-Performance Silicon-Gate CMOS
IN74HC573A
The IN74HC573A is identical in pinout to the LS/ALS573. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC573AN Plastic
IN74HC573ADW SOIC
T_A = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 20=V_CC
PIN 10 = GND
FUNCTION TABLE
Inputs
Output
Output Latch
D
Q
Enable Enable
L
H
H
H
L
H
L
L
L
L
X no change
H
X
X
Z
X = don’t care
Z = high impedance
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