IA16450 Datasheet, PDF (3/10 Pages) InnovASIC, Inc – Universal Asynchronous Receiver/Transmitter

IA16450
Page 3 of 10
Preliminary Data Sheet
Universal Asynchronous Receiver/Transmitter
I/O Signal Description
Table 1 below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided. Table 2 refers to the address
register map. Table 3 refers to the Preliminary A. C. Characteristics. Figure 2 illustrates the
Preliminary Timing Waveforms for this device. Environmental/Qualification Levels are listed in
Table 4.
Table 1
Name
MR
A(2:0)
DIN(7:0)
CS0
CS1
CS2_n
ADS_n
RD
Type
I
I
I
I
I
I
I
I
Description
Master Reset - Active high - Clears all registers (except the
receiver buffer, transmitter holding and divisor latches) to their
initial state. Resets internal control logic to its initial state
Register Address - Active high - This bus selects one of the
internal UART registers (refer to table 1). Note the state of the
divisor latch access bit (DLAB - the msb of the line control
register) must be set high to access the divisor latches and low
to access the receiver buffer or the interrupt enable register.
Data Input Bus - Active high - Serves as input data when
writing to internal UART registers.
Chip Select 0 - Active high - When CS0, CS1 and CS2 are active
the megafunction is selected. Read and write transactions to
internal UART registers are then possible.
Chip Select 1 - Active high - When CS0, CS1 and CS2 are active
the megafunction is selected. Read and write transactions to
internal UART registers are then possible.
Chip Select 2 - Active low - When CS0, CS1 and CS2 are active
the megafunction is selected. Read and write transactions to
internal UART registers are then possible.
Address Strobe - Active low - Gating signal to the Address
input latch. The positive edge of ADS_n latches the state of the
register address bus into the Address input latch. If address
signals are guaranteed to be stable for the duration of a read or
write cycle, ADS_n may be tied low thus forcing the Address
input latch to be transparent.
Read Control - Active High - when RD is high or RD_n is low
and the UART is selected, read transactions from internal
UART registers are possible.
Copyright © 1999, InnovASIC Inc.
Customer Specific IC Solutions