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SAL-XC886CLM Datasheet, PDF (95/134 Pages) Infineon Technologies AG – 8-Bit Single Chip Microcontroller | |||
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SAL-XC886CLM
Functional Description
3.16
High-Speed Synchronous Serial Interface
The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and
half-duplex synchronous communication. The serial clock signal can be generated by
the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be
received from an external master (slave mode). Data width, shift direction, clock polarity
and phase are programmable. This allows communication with SPI-compatible devices
or devices using other synchronous serial interfaces.
Features
⢠Master and slave mode operation
â Full-duplex or half-duplex operation
⢠Transmit and receive buffered
⢠Flexible data format
â Programmable number of data bits: 2 to 8 bits
â Programmable shift direction: LSB or MSB shift first
â Programmable clock polarity: idle low or high state for the shift clock
â Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
⢠Variable baud rate
⢠Compatible with Serial Peripheral Interface (SPI)
⢠Interrupt generation
â On a transmitter empty condition
â On a receiver full condition
â On an error condition (receive, phase, baud rate, transmit error)
Data is transmitted or received on lines TXD and RXD, which are normally connected to
the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave
Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input
via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin
SCLK. Transmission and reception of data are double-buffered.
Figure 31 shows the block diagram of the SSC.
Data Sheet
88
V1.0, 2010-05
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