SAL-XC886CLM Datasheet, PDF (68/134 Pages) Infineon Technologies AG – 8-Bit Single Chip Microcontroller

SAL-XC886CLM
Functional Description
3.4.3 Interrupt Priority
An interrupt that is currently being serviced can only be interrupted by a higher-priority
interrupt, but not by another interrupt of the same or lower priority. Hence, an interrupt of
the highest priority cannot be interrupted by any other interrupt request.
If two or more requests of different priority levels are received simultaneously, the
request of the highest priority is serviced first. If requests of the same priority are
received simultaneously, then an internal polling sequence determines which request is
serviced first. Thus, within each priority level, there is a second priority structure
determined by the polling sequence shown in Table 20.
Table 20 Priority Structure within Interrupt Level
Source
Level
Non-Maskable Interrupt (NMI)
(highest)
External Interrupt 0
1
Timer 0 Interrupt
2
External Interrupt 1
3
Timer 1 Interrupt
4
UART Interrupt
5
Timer 2,UART Normal Divider Overflow,
6
MultiCAN, LIN Interrupt
ADC, MultiCAN Interrupt
7
SSC Interrupt
8
External Interrupt 2, Timer 21, UART1, UART1 9
Normal Divider Overflow, MDU, CORDIC Interrupt
External Interrupt [6:3], MultiCAN Interrupt
10
CCU6 Interrupt Node Pointer 0, MultiCAN interrupt 11
CCU6 Interrupt Node Pointer 1, MultiCAN Interrupt 12
CCU6 Interrupt Node Pointer 2, MultiCAN Interrupt 13
CCU6 Interrupt Node Pointer 3, MultiCAN Interrupt 14
Data Sheet
61
V1.0, 2010-05