TLE7278-2 Datasheet, PDF (9/25 Pages) Infineon Technologies AG – Low Dropout Voltage Regulator

TLE7278-2
Block Description and Electrical Characteristics
5.1.2 Watchdog Operation
The watchdog uses a fraction of the charge pump oscillator’s clock signal as timebase. The watchdog timebase
can be adjusted using the pins WM1 and WM2 (see Figure 5). The watchdog can be turned off setting WM1 and
WM2 to high level. The timing values used this text refer to typ. values with WM1 and WM2 connected to GND
(fast watchdog and reset timing).
If the timebase is switched by changing the condition on the WM pins, the new timing is valid from the beginning
of the new period on. From this time on, the frequency on the WDI pin must be adapted.
Figure 5 shows the state diagram of the watchdog (WD) and the mode selection. After power-on, the reset output
signal at the RO pin (microcontroller reset) is kept LOW for the reset delay time T_RD of typ. 16 ms. With the LOW
to HIGH transition of the signal at RO the device starts the ignore window time t_CW (32 ms). Next the WD starts
the Watchdog Period (time frame within a trigger at WDI must occur). From now on the timing of the signal on WDI
from the micro controller must correspond the WD-Period t_WD,p correspondent the electrical characteristics and
based on the setting on the WM pins. A Re-Trigger of the WD-Period is done with a HIGH-to-LOW Transient at
the WDI-pin within the set t_WD,p.
A HIGH to LOW transition of the watchdog trigger signal on pin WDI is taken as a trigger. To avoid wrong triggering
due to parasitic glitches two HIGH samples followed by two LOW samples (sample period t_sam typ. 0.5 ms) are
decoded as a valid trigger. A reset is generated (RO goes LOW) if there is no trigger pulse during the Watchdog
Period.
V_I
V_Q
V_RT
I_Q
V_RO
Trigger
Window
WDI
T_RD
Ingnore
Wnd
Don’t care WDI
during IW
Normal operation
1. Correct Trigger
t_sam
T_RD
t_rr
t_WD,p
No Trigger
causing reset
I_{Q, WD_OFF}
I_{Q, WD_ON}
No Reset during
Current shut down
Current Controlled
WD-turn off
t
t
t
Power
Fail
t_rr
t
t
t
WM1
WM2
Watchdog
Mode
Reset Mode
L
L
Fast
Fast
L
H
Slow
Slow
H
H
L
H
Fast
Off
Slow
Slow
7278 Timing
Figure 5 Watchdog Timing Diagram, Watchdog and Reset Modes
Data Sheet
9
Rev. 1.2, 2009-04-28