TLE7278-2 Datasheet, PDF (7/25 Pages) Infineon Technologies AG – Low Dropout Voltage Regulator

TLE7278-2
General Product Characteristics
4.2
Functional Range
Pos. Parameter
Symbol
Limit Values
Unit Conditions
Min.
Max.
4.2.1 Input voltage
V_I
5.5
45
V
TLE7278-2GV50,
TLE7278-2EV50
4.2.2
4.2
45
V
TLE7278-2GV33
4.2.3
4.5
45
V
TLE7278-2GV26
4.2.4 Output Capacitor’s Requirements C_Q
470
–
for Stability
ESR(C_Q) –
3
nF
–¹⁾
Ω
–²⁾
4.2.5 Junction Temperature
T_j
-40
150
°C
–
1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
2) relevant ESR value at f = 10 kHz
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Pos. Parameter
Symbol
Limit Values
Unit Conditions
Min. Typ. Max.
Package PG-DSO-14
4.3.1 Junction to Soldering Point¹⁾
4.3.2
4.3.3
Junction to Ambient¹⁾
R_thJSP
–
R_thJA
–
–
30
–
53
–
105 –
K/W measured to group
of pins 3, 4, 5, 10,
11, 12
K/W ²⁾
K/W footprint only³⁾
4.3.4
–
74
–
K/W 300 mm² heatsink
area on PCB³⁾
4.3.5
–
65
–
K/W 600 mm² heatsink
area on PCB³⁾
Package PG-SSOP-14 Exposed Pad
4.3.6 Junction to Case¹⁾
R_thJC
–
14
–
K/W measured to
exposed pad
4.3.7
4.3.8
4.3.9
Junction to Ambient¹⁾
4.3.10
R_thJA
–
–
–
–
47
–
141 –
66
–
56
–
K/W
K/W
K/W
K/W
2)
footprint only³⁾
300 mm² heatsink
area on PCB³⁾
600 mm² heatsink
area on PCB³⁾
1) not subject to production test, specified by design
2) Specified R_thJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified R_thJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³ board with 1 copper layer (1 x 70µm Cu).
Data Sheet
7
Rev. 1.2, 2009-04-28